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Mixed-Signal Front-End (MxFETM) Baseband Transceiver for Broadband Applications AD9861
FEATURES
Receive path includes dual 10-bit analog-to-digital converters with internal or external reference, 50 MSPS and 80 MSPS versions Transmit path includes dual 10-bit, 200 MSPS digital-toanalog converters with 1x, 2x, or 4x interpolation and programmable gain control Internal clock distribution block includes a programmable phase-locked loop and timing generation circuitry, allowing single-reference clock operation 20-pin flexible I/O data interface allows various interleaved or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode Configurable through register programmability or optionally limited programmability through mode pins Independent Rx and Tx power-down control pins 64-lead LFCSP package (9 mm x 9 mm footprint) 3 configurable auxiliary converter pins
VIN+A ADC VIN-A VIN+B ADC VIN-B I/O INTERFACE CONFIGURATION BLOCK DATA MUX AND LATCH Rx DATA
FUNCTIONAL BLOCK DIAGRAM
I/O INTERFACE CONTROL FLEXIBLE I/O BUS [0:19]
LOW-PASS INTERPOLATION FILTER IOUT+A DAC IOUT-A IOUT+B DAC IOUT-B DATA LATCH AND DEMUX
Tx DATA
AUX ADC
AUX DAC ADC CLOCK AUX DAC DAC CLOCK AUX ADC PLL CLKIN
APPLICATIONS
Broadband access Broadband LAN Communications (modems)
AD9861
AUX DAC
03606-0-001
Figure 1.
GENERAL DESCRIPTION The AD9861 is a member of the MxFE family--a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC(R)). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2x or 4x interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market. The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches. A flexible, bidirectional 20-bit I/O bus accommodates a variety
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
of custom digital back ends or open market DSPs. In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects. The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format). The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm x 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9861 TABLE OF CONTENTS
Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Pin Function Descriptions...................... 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 21 Theory of Operation ...................................................................... 22 System Block ............................................................................... 22 Rx Path Block.............................................................................. 22 Tx Path Block.............................................................................. 24 Auxiliary Converters.................................................................. 27 Digital Block................................................................................ 30 Programmable Registers............................................................ 42 Clock Distribution Block .......................................................... 45 Outline Dimensions ....................................................................... 49 Ordering Guide .......................................................................... 50
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 52
AD9861 Tx PATH SPECIFICATIONS
Table 1. AD9861-50 and AD9861-80 FDAC = 200 MSPS; 4x interpolation; RSET = 4.02 k; differential load resistance of 100 1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V, unless otherwise noted
Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch Error Reference Voltage Output Capacitance Phase Noise (1 kHz Offset, 6 MHz Tone) Output Voltage Compliance Range TxPGA Gain Range TxPGA Step Size Tx PATH DYNAMIC PERFORMANCE (IOUTFS = 20 mA; FOUT = 1 MHz) SNR SINAD THD SFDR, Wideband (DC to Nyquist) SFDR, Narrowband (1 MHz Window)
1
Temp Full Full Full Full 25C Full Full Full 25C Full Full Full
Test Level IV IV IV V IV IV V V V IV V V
Min
Typ 10
Max
Unit Bits MHz mA
200 20 1% -3.5 -0.1 1.23 5 -115 -1.0 20 0.10 +1.0 +3.5 +0.1
% FS % FS V pF dBc/Hz V dB dB
Full Full Full Full Full
IV IV IV IV IV
60.2 59.7 64.6 72.5
60.8 60.7 -77.5 76.0 81.0
-65.8
dB dB dBc dBc dBc
See Figure 2 for description of the TxDAC termination scheme.
TxDAC 50 50
03606-0-030
Figure 2. Diagram Showing Termination of 100 Differential Load for Some TxDAC Measurements
Rev. 0 | Page 3 of 52
AD9861 Rx PATH SPECIFICATIONS
Table 2. AD9861-50 and AD9861-80 FADC = 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3V, unless otherwise noted
Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error Reference Voltage Reference Voltage (REFT-REFB) Error Input Resistance (Differential) Input Capacitance Input Bandwidth Differential Analog Input Voltage Range Rx PATH DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Aperature Delay Aperature Uncertainty (Jitter) Input Referred Noise AD9861-50 Rx PATH DYNAMIC PERFORMANCE (VIN = -0.5 dBFS; FIN = 10 MHz) SNR SINAD SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs AD9861-80 Rx PATH DYNAMIC PERFORMANCE (VIN = -0.5 dBFS; FIN = 10 MHz) SNR SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs Temp Full Full Full Full Full Full Full Full Full Full 25C 25C 25C 25C 25C Test Level V IV V V V IV V V V V V V V V V Min Typ 10 50/80 0.2 0.1 1.0 6 2 5 30 2 0.75 0.75 2.0 1.2 450 Max Unit Bits MSPS % FS % FS V mV k pF MHz V p-p differential LSB LSB ns ps rms uV
-30
+30
Full Full 25C Full Full Full
IV IV IV IV IV V
55.5 55.6 58.5 65.7
60 60 60 -71.5 73.5 80
-64.6
dBc dBc dBc dBc dBc dB
Full Full Full Full Full
IV IV IV IV V
55.4 52.7
59.5 59.0 -67 67 80
dBc dBc dBc dBc dB
Rev. 0 | Page 4 of 52
AD9861 POWER SPECIFICATIONS
Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3.3 V; FCLKIN = 50 MHz; PLL 4x setting; normal timing mode
Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) TxPath (2 mA Full-Scale Outputs) Rx Path (-80, at 80 MSPS) RxPath (-80, at 40 MSPS, Low Power Mode) RxPath (-80, at 20 MSPS, Ultralow Power Mode) Rx Path (-50, at 50 MSPS) RxPath (-50, at 50 MSPS, Low Power Mode) RxPath (-50, at 16 MSPS, Ultralow Power Mode) TxPath, Power-Down Mode RxPath, Power-Down Mode PLL DIGITAL SUPPLY CURRENTS TxPath, 1x Interpolation, 50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 2x Interpolation, 100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 4x Interpolation, 200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode RxPath Digital, Half-Duplex 24 Mode Temp Full Full
Full
Test Level IV IV
IV
Min 2.7 2.7
2.7
Typ
Max 3.6 3.6
3.6
Unit V V
V
Full Full Full Full Full Full Full Full Full Full Full Full
V V V V V V V V V V V V
70 20 165 82 35 103 69 28 2 5 12 20
mA mA mA mA mA mA mA mA mA mA mA mA
Full
V
50
mA
Full
V
80
mA
Full
V
15
mA
DIGITAL SPECIFICATIONS
Table 4. AD9861-50 and AD9861-80
Parameter LOGIC LEVELS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Output Logic High Voltage, VOH (1 mA Load) Output Logic Low Voltage, VOL (1 mA Load) DIGITAL PIN Input Leakage Current Input Capacitance Minimum RESET Low Pulse Width Digital Output Rise/Fall Time Temp Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV Min DRVDD - 0.7 0.4 DRVDD - 0.6 0.4 12 3 5 2.8 4 Typ Max Unit V V V V A pF Input Clock Cycles ns
Rev. 0 | Page 5 of 52
AD9861 TIMING SPECIFICATIONS
Table 5. AD9861-50 and AD9861-80
Parameter INPUT CLOCK CLKIN Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD20 Mode, Time Required Before Data Latching Edge) Hold Time (HD20 Mode, Time Required After Data Latching Edge) Latency 1x Interpolation (data in until peak output response) Latency 2x Interpolation (data in until peak output response) Latency 4x Interpolation (data in until peak output response) RxPATH DATA Output Delay (HD20 Mode, tOD) Temp Full Full Full Full Test Level IV IV IV V Min 1 16 32 5 Typ Max 200 200 350 Unit MHz MHz MHz ns (see Clock Distribution Block section) ns (see Clock Distribution Block section) DAC Clock Cycles DAC Clock Cycles DAC Clock Cycles ns (see Clock Distribution Block section) ADC Clock Cycles
Full
V
-1.5
Full Full Full Full
V V V V
7 35 83 -1.5
Latency
Full
V
5
Table 6. Explanation of Test Levels
Level I II III IV V VI Description 100% production tested. 100% production tested at 25C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 6 of 52
AD9861 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Electrical AVDD Voltage DRVDD Voltage Analog Input Voltage Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating 3.9 V max 3.9 V max -0.3 V to AVDD + 0.3 V -0.3 V to DVDD - 0.3 V 5 mA max -40C to +85C 150C 300C -65C to +150C
Thermal Resistance 64-lead LFCSP (4-layer board): JA = 24.2 (paddle soldered to ground plan, 0 LPM Air) JA = 30.8 (paddle not soldered to ground plan, 0 LPM Air)
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 52
AD9861 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
SPI_CS TxPWRDWN RxPWRDWN ADC_AVDD REFT ADC_AVSS VIN+A VIN-A VREF VIN-B VIN+B ADC_AVSS REFB ADC_AVDD PLL_AVDD PLL_AVSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SPI_DIO SPI_CLK SPI_SDO/AUX_SPI_SDO ADC_LO_PWR/AUX_SPI_CS DVDD DVSS AVDD IOUT-A IOUT+A AGND REFIO FSADJ AGND IOUT+B IOUT-B AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 CLKIN 47 AUXADC_REF 46 RESET 45 AUX_DACC/AUX_ADCB 44 L0 43 L1
AD9861
TOP VIEW (Not to Scale)
42 L2 41 L3 40 L4 39 L5 38 L6 37 L7 36 L8 35 L9 34 AUX_SPI_CLK 33 IFACE1
IFACE2 IFACE3 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 AUX_DACA/AUX_ADCA2 AUX_DACB/AUX_ADCA1 DRVDD DRVSS
03606-0-019
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. 1 2 3 4 5, 31 6, 32 7, 16, 50, 51, 61 8, 9 10, 13, 49, 53, 59 11 12 14, 15 17 18 19-28 29 30 33 Name1 SPI_DIO (Interp1) SPI_CLK (Interp0) SPI_SDO/AUXSPI_SDO (FD/HD) ADC_LO_PWR/AUX_SPI_CS DVDD DVSS AVDD IOUT-A, IOUT+A AGND, AVSS REFIO FSADJ IOUT+B, IOUT-B IFACE2 (10/20) IFACE3 U9-U0 AUX1 AUX2 IFACE1 Description2, 3 SPI: Serial Port Data Input. No SPI: Tx Interpolation Pin, MSB. SPI: Serial Port Shift Clock. No SPI: Tx Interpolation Pin, LSB. SPI: 4-Wire Serial Port Data Output/Data Output Pin for AuxSPI. No SPI: Configures Full-Duplex or Half-Duplex Mode. ADC Low Power Mode Enable. Defined at power-up. CS for AuxSPI. Digital Supply. Digital Ground. Analog Supply. DAC A Differential Output. Analog Ground. Tx DAC Band Gap Reference Decoupling Pin. Tx DAC Full-Scale Adjust Pin. DAC B Differential Output. SPI: Buffered CLKIN. Can be configured as system clock output. No SPI: For FD: Buffered CLKIN; For HD20 or HD10 : 10/20 Configuration Pin. Clock Output. Upper Data Bit 9 to Upper Data Bit 0. Configurable as either AuxADC_A2 or AuxDAC_A. Configurable as either AuxADC_A1 or AuxDAC_B. SPI: For FD: TxSYNC; For HD20, HD10, or Clone: Tx/Rx. No SPI: FD >> TxSYNC; HD20 or HD10: Tx/Rx.
Rev. 0 | Page 8 of 52
AD9861
Pin No. 34 35-44 45 46 47 48 52 54, 55 56 57, 58 60 62 63 64
1 2
Name1 AUX_SPI_CLK L9-L0 AUX3 RESET AUX_ADC_REF CLKIN REFB VIN+B, VIN-B VREF VIN-A, VIN+A REFT RxPwrDwn TxPwrDwn SPI_CS
Description2, 3 CLK for AuxSPI. Lower Data Bit 9 to Lower Data Bit 0. Configurable as either AuxADC_B or AuxDAC_C. Chip Reset When Low. Decoupling for AuxADC On-Chip Reference. Clock Input. ADC Bottom Reference. ADC B Differential Input. ADC Band Gap Reference. ADC A Differential Input. ADC Top Reference. Rx Analog Power-Down Control. Tx Analog Power-Down Control. SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: Tie low to disable SPI and use mode pins. This pin must be tied low.
Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as no SPI mode. Pin function depends if the serial port is used to configure the AD9861 (called SPI mode) or if mode pins are used to configure the AD9861 (called No SPI mode). The differences are indicated by the SPI and No SPI labels in the description column. 3 Some pin descriptions depend on the interface configuration, full-duplex (FD), half-duplex interleaved data (HD10), half-duplex parallel data (HD20), and a half-duplex interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface.
Rev. 0 | Page 9 of 52
AD9861 TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
03606-0-031
0 -10 -20 -30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-032
-100 -110 0 5 15 10 FREQUENCY (MHz) 20 25
Figure 4. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone
0 -10 -20 -30
Figure 7. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 1 MHz and 2 MHz Tones
0 -10 -20 -30
AMPLITUDE (dBFS)
03606-0-033
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-034
Figure 5. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 5 MHz Tone
Figure 8. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz and 8 MHz Tones
0 -10 -20 -30
0 -10 -20 -30
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
03606-0-035
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-036
-100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 6. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 24 MHz Tone
Figure 9. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 20 MHz and 25 MHz Tones
Rev. 0 | Page 10 of 52
AD9861
0 -10 -20 -30 0 -10 -20 -30
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
03606-0-037
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-038
-100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 76 MHz Tone
Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 70 MHz and 72 MHz Tones
62
NORMAL POWER @ 50MSPS
62
NORMAL POWER @ 50MSPS
10.0 9.8
LOW POWER ADC @ 25MSPS 59
59
LOW POWER ADC @ 25MSPS
9.6 9.4
SINAD (dBc)
SNR (dBc)
9.2 56 9.0 8.8 ULTRALOW POWER ADC @ 16MSPS 8.6 8.4 8.2 50 0 5 15 10 INPUT FREQUENCY (MHz) 20 8.0 25
56
53
ULTRALOW POWER ADC @ 16MSPS
53
03606-0-039
50 0 5 15 10 INPUT FREQUENCY (MHz) 20 25
Figure 11. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency
Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. Input Frequency
80
LOW POWER ADC @ 25MSPS
-50
75 NORMAL POWER @ 50MSPS
-55
70
-60
SFDR (dBc)
THD (dBc)
ULTRALOW POWER ADC @ 16MSPS -65 NORMAL POWER @ 50MSPS
65
60 ULTRALOW POWER ADC @ 16MSPS
03606-0-041
-70
LOW POWER ADC @ 25MSPS -80 0 5 10 15 INPUT FREQUENCY (MHz) 20 25
50 0 5 10 15 INPUT FREQUENCY (MHz) 20 25
Figure 12. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency
Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency
Rev. 0 | Page 11 of 52
03606-0-042
55
-75
03606-0-040
ENOB (Bits)
AD9861
70 60 50
90 SFDR 80 70 -80 -70 -60 -50 -40 -90
SFDR (dBFS)
40 IDEAL SNR 30 SNR 20 10 0 0 -5 -10 -15 -20 -25 -30 INPUT AMPLITUDE (dBFS) -35 -40
60 50 40 30 20 0 -5 -10 -15 -20 -25 -30 INPUT AMPLITUDE (dBFS) -35
-45
-20 -40
Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude
Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone THD and SFDR Performance vs. Input Amplitude
62 AVE (-40C) 61 AVE (+25C) 60
62
10.0 9.9
61
AVE (-40C) AVE (+25C)
9.8 9.7
60
SINAD (dBc)
SNR (dBc)
59
AVE (+85C)
59
AVE (+85C)
9.5 9.4
58
58
9.3 9.2 9.1
03606-0-046
03606-0-045
57
57
56 2.7
3.0 3.3 ADC_AVDD VOLTAGE (V)
3.6
56 2.7
3.0 3.3 ADC_AVDD VOLTAGE (V)
9.0 3.6
Figure 17. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. ADC_AVDD and Temperature
-70.0 -70.5 -71.0 -71.5 AVE (+85C)
Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. ADC_AVDD and Temperature
70 71 72 AVE (+85C) 73 74 AVE (+25C) 75 AVE (-40C) 76
03606-0-047
THD (dBc)
-72.0 AVE (+25C) -72.5 -73.0 -73.5 AVE (-40C) -74.0 -74.5 -75.0 3.6 3.3 3.0 INPUT AMPLITUDE (dBFS)
SFDR (dBc)
77 78 3.6
2.7
3.3 3.0 INPUT AMPLITUDE (dBFS)
2.7
Figure 18. AD9861-50 Rx Path Single-Tone THD Performance vs. ADC_AVDD and Temperature
Figure 21. AD9861-50 Rx Path Single-Tone SFDR Performance vs. ADC_AVDD and Temperature
Rev. 0 | Page 12 of 52
03606-0-048
ENOB (Bits)
9.6
03606-0-044
03606-0-043
-30
THD (dBFS)
THD
SNR (dBc)
AD9861
0 -10 -20 -30 0 -10 -20 -30
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
03606-0-049
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-050
-100 -110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure 22. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone
Figure 25. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 1 MHz and 2 MHz Tones
0 -10 -20 -30
0 -10 -20 -30
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
03606-0-051
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-052
-100 -110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure 23. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 5 MHz Tone
Figure 26. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz and 8 MHz Tones
0 -10 -20 -30
0 -10 -20 -30
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
03606-0-053
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-054
-100 -110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure 24. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 24 MHz Tone
Figure 27. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 20 MHz and 25 MHz Tones
Rev. 0 | Page 13 of 52
AD9861
62 LOW POWER ADC @ 40MSPS ULTRALOW POWER ADC @ 16MSPS 62 LOW POWER ADC @ 40MSPS 9.8 ULTRALOW POWER ADC @ 16MSPS 9.6 59 NORMAL POWER @ 80MSPS
SINAD (dBc)
10.0
59 9.4
ENOB (Bits)
03606-0-058
SNR (dBc)
NORMAL POWER @ 80MSPS 56
9.2 9.0 8.8 8.6
56
53
03606-0-055
53 8.4 8.2 50 0 5 10 15 20 INPUT FREQUENCY (MHz) 25 8.0 30
03606-0-056
50 0 5 10 15 20 INPUT FREQUENCY (MHz) 25 30
Figure 28. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency and Power Setting
Figure 31. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SINAD Performance vs. Input Frequency and Power Setting
85 LOW POWER ADC @ 40MSPS 80 ULTRALOW POWER ADC @ 16MSPS SFDR (dBc) THD (dBc) 75
-50
-55
-60
-65 LOW POWER ADC @ 40MSPS -70
70 NORMAL POWER @ 80MSPS 65
03606-0-057
-75 NORMAL POWER @ 80MSPS -80 0 5 ULTRALOW POWER ADC @ 16MSPS 20 25
60 0 5 10 15 INPUT FREQUENCY (MHz) 20 25
10 15 INPUT FREQUENCY (MHz)
Figure 29. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency and Power Setting
Figure 32. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency and Power Setting
70 60 50
-80
80
-70
70
-60
SFDR
60
40 IDEAL SNR 30 20 10 0 0 -5 -10 -15 -20 -25 -30 INPUT AMPLITUDE (dBFS) -35 -40
-50 THD
50
-40
40
SNR
03606-0-059 03606-0-060
-30
30
-20 0 -5 -10 -15 -20 -25 -30 INPUT AMPLITUDE (dBFS) -35
-45
20 -40
Figure 30. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude
Figure 33. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. Input Amplitude
Rev. 0 | Page 14 of 52
SFDR (dBFS)
THD (dBFS)
SNR (dBc)
AD9861
62 62 10.0 9.9 61 AVE (+85C) 60
SINAD (dBc) SNR (dBc)
61 AVE (-40C) 60 AVE (+85C) 59 AVE (+25C)
9.8 9.7 9.6 9.5 9.4
ENOB (Bits)
03606-0-066
59 AVE (+25C) 58
58 AVE (-40C)
03606-0-065
9.3 9.2 9.1
57
57
56 2.7
3.0 3.3 ADC_AVDD VOLTAGE (V)
3.6
56 2.7
3.0 3.3 ADC_AVDD VOLTAGE (V)
9.0 3.6
Figure 34. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. AVDD and Temperature
Figure 37. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SINAD Performance vs. AVDD and Temperature
70 69 68 67 AVE (+25C) AVE (-40C)
65 AVE (+85C) 66 67 68 AVE (+25C) AVE (-40C)
65 AVE (+85C) 64 63 62 61 60 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V)
03606-0-061
SFDR (dBc)
THD (dBc)
66
69 70 71 72 73 74 75 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V)
03606-0-062
3.6
3.6
Figure 35. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. AVDD and Temperature
Figure 38. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SFDR Performance vs. AVDD and Temperature
120 NORM 100
180 160
NORM
ADC AVDD CURRENT (mA)
ADC AVDD CURRENT (mA)
140 120 100 LP 80 60 40 20 0 0 10 20 30 40 50 FCLK (MHz) 60 70 80 ULP
03606-0-064
80 LP 60
40 ULP
03606-0-063
20
0 0 10 20 30 FCLK (MHz) 40 50
Figure 36. AD9861-50 ADC_AVDD Current vs. Sampling Rate for Different ADC Power Levels
Figure 39. AD9861-80 ADC_AVDD Current vs. ADC Sampling Rate for Different ADC Power Levels
Rev. 0 | Page 15 of 52
AD9861
0 -10 -20 -30 0 -10 -20 -30
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90
03606-0-068
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-069
-100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 40. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Differential Load
Figure 43. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Differential Load
0 -10 -20 -30
0 -10 -20 -30
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90
03606-0-070
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-071
-100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 41. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Differential Load
Figure 44. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Differential Load
0 -10 -20 -30
0 -10 -20 -30
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90
03606-0-072
AMPLITUDE (dBc)
-40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-073
-100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 42. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 2 mA Full-Scale Output into 600 Differential Load
Figure 45. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 2 mA Full-Scale Output into 600 Differential Load
Rev. 0 | Page 16 of 52
AD9861
-50 -50
-60
-60
THD (dBc)
-80
THD (dBc)
03606-0-074
-70
-70
-80
-90
-90
03606-0-075
-100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
-100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
Figure 46. AD9861 Tx Path THD vs. Output Frequency of Tx Path with 20 mA Full-Scale Output into 60 Differential Load
Figure 49. AD9861 Tx Path THD vs. Output Frequency of Tx Path with 2 mA Full-Scale Output into 600 Differential Load
62
62
61
61
60
60
SINAD (dBc)
59
SINAD (dBc)
03606-0-076
59
58
58
56 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
56 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
Figure 47. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Differential Load
Figure 50. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 2 mA Full-Scale Output into 600 Differential Load
-70
-70
-75
-75
IMD (dBc)
-85
IMD (dBc)
-80
-80
-85
-90
03606-0-078
-90
03606-0-079
-95 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
-95 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25
Figure 48. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Differential Load
Figure 51. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency of Tx Path, with 2 mA Full-Scale Output into 600 Differential Load
Rev. 0 | Page 17 of 52
03606-0-077
57
57
AD9861
Figure 52 to Figure 57 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The center two carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
-30 -40 -50 -30 -40 -50
AMPLITUDE (dBc)
-70 -80 -90 -100 -110
03606-0-080
AMPLITUDE (dBc)
-60
-60 -70 -80 -90 -100 -110 -120 -130 18.75 19.25 19.75 20.25 FREQUENCY (MHz) 20.75
03606-0-081
-120 -130 7.5 12.5 17.5 22.5 FREQUENCY (MHz) 27.5
32.5
21.25
Figure 52. AD9861 Tx Path FFT, 64-Carrier (Center Two Carriers Removed) OFDM Signal over 20 MHz Bandwidth, Centered at 20 MHz, with 20 mA Full-Scale Output into 60 Differential Load
-30 -40 -50
Figure 55. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 52
-30 -40 -50
AMPLITUDE (dBc)
-70 -80 -90 -100 -110
03606-0-082
AMPLITUDE (dBc)
-60
-60 -70 -80 -90 -100 -110 -120 -130 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 FREQUENCY (MHz) 31.5 32.0
03606-0-083
-120 -130 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 FREQUENCY (MHz) 11.5 12.0
12.5
32.5
Figure 53. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 52
Figure 56. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 52
-30 -40 -50
-30 -40 -50
AMPLITUDE (dBc)
-70 -80 -90 -100 -110
03606-0-084
AMPLITUDE (dBc)
-60
-60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80
03606-0-085
-120 -130 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80
Figure 54. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1x Interpolation
Figure 57. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 4x Interpolation
Rev. 0 | Page 18 of 52
AD9861
Figure 58 to Figure 63 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
-40 -50 -60 -40 -50 -60
AMPLITUDE (dBc)
-80 -90 -100 -110 -120 -130 -140 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 FREQUENCY (MHz) 7.6 7.8
03606-0-086
AMPLITUDE (dBc)
-70
-70 -80 -90 -100 -110 -120 -130 -140 6.97 6.98 6.99 7.00 7.01 FREQUENCY (MHz) 7.02
03606-0-087
8.0
7.03
Figure 58. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) OFDM Signal over 1.75 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Differential Load
-40 -50 -60
Figure 61. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 58
-40 -50 -60
AMPLITUDE (dBc)
-80 -90 -100 -110 -120 -130 -140 6.06 6.08 6.10 6.12 6.14 FREQUENCY (MHz) 6.16 6.18
03606-0-088
AMPLITUDE (dBc)
-70
-70 -80 -90 -100 -110 -120 -130 -140 7.81 7.83 7.85 7.87 7.89 FREQUENCY (MHz) 7.91 7.93
03606-0-089
Figure 59. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 58
-30 -40 -50 -60
AMPLITUDE (dBc)
Figure 62. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 52
-30 -40 -50 -60
AMPLITUDE (dBc)
03606-0-090
-70 -80 -90 -100 -110 -120 -130 0 5 10 15 FREQUENCY (MHz) 20 25
-70 -80 -90 -100 -110 -120 -130 0 5 10 15 FREQUENCY (MHz) 20 25
03606-0-091
Figure 60. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1x Interpolation
Figure 63. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 4x Interpolation
Rev. 0 | Page 19 of 52
AD9861
Figure 64 to Figure 69 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output.
-40 -50 -60
-40 -50 -60
AMPLITUDE (dBc)
03606-0-092
AMPLITUDE (dBc)
-70 -80 -90 -100 -110 -120 -130 -140 9 14 19 24 FREQUENCY (MHz) 29 34
-70 -80 -90 -100 -110 -120 -130 -140 22.6 22.7 22.8 22.9 23.0 23.1 FREQUENCY (MHz) 23.2 23.3
03606-0-093
23.4
Figure 64. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) OFDM Signal over 23 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Differential Load
-40 -50 -60
Figure 67. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 64
-40 -50 -60 -70
AMPLITUDE (dBc)
03606-0-094
AMPLITUDE (dBc)
-70 -80 -90 -100 -110 -120 -130 -140 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 FREQUENCY (MHz) 12.1 12.3
-80 -90 -100 -110 -120 -130 -140 33.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 FREQUENCY (MHz) 35.1 35.3
03606-0-095
12.5
35.5
Figure 65. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 64
-30 -40 -50
Figure 68. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 64
-30 -40 -50
AMPLITUDE (dBc)
-70 -80 -90 -100 -110
03606-0-096
AMPLITUDE (dBc)
-60
-60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90
03606-0-097
-120 -130 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90
Figure 66. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 1x Interpolation
Figure 69. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 4x Interpolation
Rev. 0 | Page 20 of 52
AD9861 TERMINOLOGY
Input Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the CLKIN signal and the instant at which the analog input is actually sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a -0.5 dBFS signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the input phase 180 and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) The effective number of bits is calculated from the measured SNR based on the following equation:
ENOB = SNRMEASURED - 1.76 dB 6.02
Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of an LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full-scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (i.e., always related back to converter full scale). SFDR does not include harmonic distortion components. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc.
Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that a signal should be left in the logic high state to achieve rated performance; pulse width low is the minimum time a signal should be left in the low state, logic low. Full-Scale Input Power Expressed in dBm, full-scale input power is computed using the following equation:
V 2 Z Power FULLSCALE = 10 log FULLSCALE - RMS INPUT 0.001

Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC.
Rev. 0 | Page 21 of 52
AD9861 THEORY OF OPERATION
SYSTEM BLOCK
The AD9861 is targeted to cover the mixed-signal front end needs of multiple wireless communication systems. It features a receive path that consists of dual 10-bit receive ADCs, and a transmit path that consists of dual 10-bit transmit DACs (TxDAC). The AD9861 integrates additional functionality typically required in most systems, such as power scalability, additional auxiliary converters, Tx gain control, and clock multiplication circuitry. The AD9861 minimizes both size and power consumption to address the needs of a range of applications from the low power portable market to the high performance base station market. The part is provided in a 64-lead lead frame chip scale package (LFCSP) that has a footprint of only 9 mm x 9 mm. Power consumption can be optimized to suit the particular application beyond just a speed grade option by incorporating power-down controls, low power ADC modes, TxDAC power scaling, and a half-duplex mode, which automatically disables the unused digital path. The AD9861 uses two 10-bit buses to transfer Rx path data and Tx path data. These two buses support 20-bit parallel data transfers or 10-bit interleaved data transfers. The bus is configurable through either external mode pins or through internal registers settings. The registers allow many more options for configuring the entire device. The following sections discuss the various blocks of the AD9861: Rx block, Tx block, the auxiliary converters, the digital block, programmable registers and the clock distribution block. The differential input stage is dc self-biased and allows differential or single-ended inputs. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The latency of the Rx path is about 5 clock cycles.
Rx Path Analog Input Equivalent Circuit
The Rx path analog inputs of the AD9861 incorporate a novel structure that merges the function of the input sample-andhold amplifiers (SHAs) and the first pipeline residue amplifiers into a single, compact switched capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. Figure 70 illustrates the equivalent analog inputs of the AD9861 (a switched capacitor input). Bringing CLK to logic high opens switch S3 and closes switches S1 and S2; this is the sample mode of the input circuit. The input source connected to VIN+ and VIN- must charge capacitor CH during this time. Bringing CLK to a logic low opens S2, and then switch S1 opens followed by closing S3. This puts the input circuit into hold mode.
S1 VIN+ RIN VCM RIN VIN- CIN
03606-0-002
CH +
CIN S3 CH - S2
Rx PATH BLOCK
Rx Path General Description
The AD9861 Rx path consists of two 10-bit, 50 MSPS (for the AD9861-50) or 80 MSPS (for the AD9861-80) analog-to-digital converters (ADCs). The dual ADC paths share the same clocking and reference circuitry to provide optimal matching characteristics. Each of the ADCs consists of a 9-stage differential pipelined switched capacitor architecture with output error correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the falling edge of the input clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage's input signal, and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
Figure 70. Differential Input Architecture
The structure of the input SHA places certain requirements on the input drive source. The differential input resistors are typically 2 k each. The combination of the pin capacitance, CIN, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one-half of a clock cycle. When the SHA goes into sample mode, the input source must charge or discharge capacitor CH from the voltage already stored on it to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON of switch S1 (typically 100 ) to a settled voltage within one-half of the ADC sample period. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high.
Rev. 0 | Page 22 of 52
AD9861
Rx Path Application Section
Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal source. Figure 71 shows this configuration.
AD9861
RSERIES VIN+ CSHUNT VIN- RSERIES
03606-0-003
default 1 V VREF reference accepts a 2 V p-p differential input swing and the offset voltage should be
REFT = AVDD/2 + 0.5 V REFB = AVDD/2 - 0.5 V
AD9861
REFT 0.1F TO ADCs REFB 0.1F VREF 10F 0.1F 0.1F 10F
Figure 71. Typical Input
The bandwidth of the particular application limits the size of this resistor. For applications with signal bandwidths less than 10 MHz, the user may insert series input resistors and a shunt capacitor to produce a low-pass filter for the input signal. Additionally, adding a shunt capacitance between the VIN pins can lower the ac load impedance. The value of this capacitance depends on the source resistance and the required signal bandwidth. The Rx input pins are self-biased to provide this midsupply, common-mode bias voltage, so it is recommended to ac couple the signal to the inputs using dc blocking capacitors. In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9861. The inputs accept a signal with a 2 V p-p differential input swing centered about one-half of the supply voltage (AVDD/2). If the dc bias is supplied externally, the internal input bias circuit should be powered down by writing to registers Rx_A dc bias [Register 0x3, Bit 6] and Rx_B dc bias [Register 0x4, Bit 7]. The ADCs in the AD9861 are designed to sample differential input signals. The differential input provides improved noise immunity and better THD and SFDR performance for the Rx path. In systems that use single-ended signals, these inputs can be digitized, but it is recommended that a single-ended-todifferential conversion be performed. A single-ended-todifferential conversion can be performed by using a transformer coupling circuit (typically for signals above 10 MHz) or by using an operational amplifier, such as the AD8138 (typically for signals below 10 MHz).
0.5V
03606-0-020
Figure 72. Typical Rx Path Decoupling
An external reference may be used for systems that require a different input voltage range, high accuracy gain matching between multiple devices, or improvements in temperature drift and noise characteristics. When an external reference is desired, the internal Rx band gap reference must be powered down using the VREF2 register [Register 0x5, Bit 4] and the external reference driving the voltage level on the VREF pin. The external voltage level should be one-half of the desired peak-topeak differential voltage swing. The result is that the differential voltage references are driven to new voltages:
REFT = AVDD/2 +VREF/2 V REFB = AVDD/2 - VREF/2 V
If an external reference is used, it is recommended not to exceed a differential offset voltage for the reference greater than 1 V.
Clock Input and Considerations
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9861 contains clock duty cycle stabilizer circuitry (DCS). The DCS retimes the internal ADC clock (nonsampling edge) and provides the ADC with a nominal 50% duty cycle. Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Conversely, DCS should not be used for Rx sampling below 40 MSPS. Maintaining a 50% duty cycle clock is particularly important in high speed applications when proper sample-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by writing highs to the Rx_A/Rx_B CLK duty register bits [Register 0x06/0x07, Bit 4]. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 s to 3 s to allow the DLL to adjust to the new rate and settle. High speed, high resolution ADCs are sensitive to the quality of the clock input. The
ADC Voltage References
The AD9861 10-bit ADCs use internal references that are designed to provide for a 2 V p-p differential input range. The internal band gap reference generates a stable 1 V reference level and is decoupled through the VREF pin. REFT and REFB are the differential references generated based on the voltage level of VREF. Figure 72 shows the proper decoupling of the reference pins VREF, REFT, and REFB when using the internal reference. Decoupling capacitors should be placed as close to the reference pins as possible. External references REFT and REFB are centered at AVDD/2 with a differential voltage equal to the voltage at VREF (by default 1 V when using the internal reference), allowing a peakto-peak differential voltage swing of 2x VREF. For example, the
Rev. 0 | Page 23 of 52
AD9861
degradation in SNR at a given full-scale input frequency (fINPUT), due only to aperture jitter (tA), can be calculated with the following equation:
SNR degradation = 20 log [(1/2)FINtA)]
In the equation, the rms aperture jitter, tA, represents the rootsum-square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the AD9861. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
3, 4, and 5. Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 F and 10 F decoupling capacitors on REFT and REFB.
Tx PATH BLOCK
The AD9861 transmit (Tx) path includes dual interpolating 10-bit current output DACs that can be operated independently or can be coupled to form a complex spectrum in an image reject transmit architecture. Each channel includes two FIR filters, making the AD9861 capable of 1x, 2x, or 4x interpolation. High speed input and output data rates can be achieved within the limitations of Table 9.
Table 9. AD9861 Tx Path Maximum Data Rate
Input Data Rate per Channel (MSPS) 80 160 80 80 50 50 DAC Sampling Rate (MSPS) 80 160 160 160 200 200
Power Dissipation and Standby Mode
The power dissipation of the AD9861 Rx path is proportional to its sampling rate. The Rx path portion of the digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by
IDRVDD = VDRVDD x CLOAD x fCLOCK x N
Interpolation Rate 1x 2x 4x
20-Bit Interface Mode FD, HD10, Clone HD20 FD, HD10, Clone HD20 FD, HD10, Clone HD20
where N is the number of bits changing and CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates, which increases with clock frequency. The baseline power dissipation for either speed grade can be reduced by asserting the ADC_LO_PWR pin, which reduces internal ADC bias currents by half, in some case resulting in degraded performance. To further reduce power consumption of the ADC, the ADC_LO_PWR pin can be combined with a serial programmable register setting to configure an ultralow power mode. The ultralow power mode reduces the power consumption by a fourth of the normal power consumption. The ultralow power mode can be used at slower sampling frequencies or if reduced performance is acceptable. To configure the ultralow power mode, assert the ADC_LO_PWR pin and write the following register settings: Register 0x08 Register 0x09 Register 0x0A (MSB) `0000 1100' (MSB) `0111 0000' (MSB) `0111 0000'
By using the dual DAC outputs to form a complex signal, an external analog quadrature modulator, such as the Analog Devices AD8349, can enable an image rejection architecture. (Note: the AD9861 evaluation board includes a quadrature modulator in the Tx path that accommodates the AD8345, AD8346 and the AD8345 footprints.) To optimize the image rejection capability, as well as LO feedthrough suppression in this architecture, the AD9861 offers programmable (via the SPI port) fine (trim) gain and offset adjustment for each DAC. Also included in the AD9861 are a phase-locked loop (PLL) clock multiplier and a 1.2 V band gap voltage reference. With the PLL enabled, a clock applied to the CLKIN input is multiplied internally and generates all necessary internal synchronization clocks. Each 10-bit DAC provides two complementary current outputs whose full-scale currents can be determined from a single external resistor. An external pin, TxPWRDWN, can be used to power down the Tx path, when not used, to optimize system power consumption. Using the TxPWRDWN pin disables clocks and some analog circuitry, saving both digital and analog power. The power-down mode leaves the biases enabled to facilitate a quick recovery time, typically <10 s. Additionally, a sleep mode is available, which turns off the DAC output current, but leaves all other circuits active, for a modest power savings. An SPI compliant serial port is used to program the many features of the AD9861. Note that in power-down mode, the SPI port is still active.
Either of the ADCs in the AD9861 Rx path can be placed in standby mode independently by writing to the appropriate SPI register bits in Registers 3, 4, and 5. The minimum standby power is achieved when both channels are placed in full powerdown mode using the appropriate SPI register bits in Registers
Rev. 0 | Page 24 of 52
AD9861
DAC Equivalent Circuits
The AD9861 Tx path consisting of dual 10-bit DACs is shown in Figure 73. The DACs integrate a high performance TxDAC core, a programmable gain control through a programmable gain amplifier (TxPGA), coarse gain control, and offset adjustment and fine gain control to compensate for system mismatches. Coarse gain applies a gross scaling to either DAC by 1x, (1/2)x, or (1/11)x. The TxPGA provides gain control from 0 dB to -20 dB in steps of 0.1 dB and is controlled via the 8-bit TxPGA setting. A fine gain adjustment of 4% for each channel is controlled through a 6-bit fine gain register. By default, coarse gain is 1x, the TxPGA is set to 0 dB, and the fine gain is set to 0%. The TxDAC core of the AD9861 provides dual, differential, complementary current outputs generated from the 10-bit data. The 10-bit dual DACs support update rates up to 200 MSPS. The differential outputs (IOUT+ and IOUT-) of each dual DAC are complementary, meaning that they always add up to the fullscale current output of the DAC, IOUTFS. Optimum ac performance loads or a transformer.
OFFSET DAC + TxDAC PGA + + + IOUT+A IOUT-A
1.2V REFERENCE
DAC A AND DAC B REFERENCE BIASES IOUTFSMAX
REFIO CURRENT SOURCE ARRAY FSADJ 0.1F RSET 4k
03606-0-005
IREF
Figure 74. Reference Circuitry
Referring to the transfer function of the following equation, IOUTFSMAX is the maximum current output of the DAC with the default gain setting (0 dB), and is based on a reference current, IREF. IREF is set by the internal 1.2 V reference and the external RSET resistor.
IOUTFSMAX = 64 x (REFIO/RSET)
Typically, RSET is 4 k, which sets IOUTFSMAX to 20 mA, the optimal dynamic setting for the TxDACs. Increasing RSET by a factor of 2 proportionally decreases IOUTFSMAX by a factor of 2. IOUTFSMAX of each DAC can be rescaled either simultaneously using the TxPGA gain register or independently using the DAC A/DAC B coarse gain registers. The TxPGA function provides 20 dB of simultaneous gain range for both DACs, and is controlled by writing to the SPI register TxPGA gain for a programmable full-scale output of 10% to 100% of IOUTFSMAX. The gain curve is linear in dB, with steps of about 0.1 dB. Internally, the gain is controlled by changing the main DAC bias currents with an internal TxPGA DAC whose output is heavily filtered via an on-chip R-C filter to provide continuous gain transitions. Note that the settling time and bandwidth of the TxPGA DAC can be improved by a factor of 2 by writing to the TxPGA fast register. Each DAC has independent coarse gain control. Coarse gain control can be used to accommodate different IOUTFS from the dual DACs. The coarse full-scale output control can be adjusted by using the DAC A/DAC B coarse gain registers to 1/2 or 1/11 of the nominal full-scale current. Fine gain controls and dc offset controls can be used to compensate for mismatches (for system level calibration), allowing improved matching characteristics of the two Tx channels and aiding in suppressing LO feedthrough. This is especially useful in image rejection architectures. The 10-bit dc offset control of each DAC can be used independently to provide an offset of up to 12% of IOUTFSMAX to either differential pin, thus allowing calibration of any system offsets. The fine gain control with 5-bit resolution allows the IOUTFSMAX of each DAC to be varied over a 4% range, allowing compensation of any DAC or system gain mismatches. Fine gain control is set through the DAC A/DAC B fine gain registers, and the offset control of each DAC is accomplished using the DAC A/DAC B offset registers.
REFERENCE BIAS
+ TxDAC PGA + + OFFSET DAC +
IOUT+B IOUT-B
03606-0-004
Figure 73. TxDAC Output Structure Block Diagram
The fine gain control provides improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. The independent DAC A and DAC B offset control adds a small dc current to either IOUT+ or IOUT- (not both). The selection of which IOUT this offset current is directed toward is programmable via register setting. Offset control can be used for suppression of an LO leakage signal that typically results at the output of the modulator. If the AD9861 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9861 as well as the input offset on the modulator. The reference circuitry is shown in Figure 74.
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AD9861
Clock Input Configuration
The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry provides the AD9861 with a low jitter clock input that meets the min/max logic levels while providing fast edges. When a driver is used to buffer the clock input, it should be placed very close to the AD9861 clock input, thereby negating any transmission line effects such as reflections due to mismatch. The sleep mode, when activated, turns off the DAC output currents, but the rest of the chip remains functioning. When coming out of sleep mode, the AD9861 immediately returns to full operation. A full power-down mode can be enabled through the SPI register, which turns off all Tx path related analog and digital circuitry in the AD9861. When returning from full power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle.
Programmable PLL
CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled). The PLL clock multiplier and distribution circuitry produce the necessary internal timing to synchronize the rising edge triggered latches for the enabled interpolation filters and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), and clock distribution block, all under SPI port control. The charge pump, phase detector, and VCO are powered from PLL_AVDD, while the clock distribution circuits are powered from the DVDD supply. To ensure optimum phase noise performance from the PLL clock multiplier circuits, PLL_AVDD should originate from a clean analog supply. The speed of the VCO within the PLL also has an effect on phase noise. The PLL locks with VCO speeds as low as 32 MHz up to 350 MHz, but optimal phase noise with respect to VCO speed is achieved by running it in the range of 64 MHz to 200 MHz.
Interpolation Stage
Interpolation filters are available for use in the AD9861 transmit path, providing 1x (bypassed), 2x, or 4x interpolation. The interpolation filters effectively increase the Tx data rate while suppressing the original images. The interpolation filters digitally shift the worst-case image further away from the desired signal, thus reducing the requirements on the analog output reconstruction filter. There are two 2x interpolation filters available in the Tx path. An interpolation rate of 4x is achieved using both interpolation filters; an interpolation rate of 2x is achieved by enabling only the first 2x interpolation filter. The first interpolation filter provides 2x interpolation using a 39-tap filter. It suppresses out-of-band signals by 60 dB or more and has a flat pass-band response (less than 0.1 dB ripple) extending to 38% of the input Tx data rate (19% of the DAC update rate, fDAC). The maximum input data rate is 80 MSPS per channel when using 2x interpolation. The second interpolation filter provides an additional 2x interpolation for an overall 4x interpolation. The second filter is a 15-tap filter, which suppresses out-of-band signals by 60 dB or more. The flat pass-band response (less than 0.1 dB attenuation) is 38% of the Tx input data rate (9.5% of fDAC). The maximum input data rate per channel is 50 MSPS per channel when using 4x interpolation.
Power Dissipation
The AD9861 Tx path power is derived from three voltage supplies: AVDD, DVDD, and DRVDD. IDRVDD and IDVDD are very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. IAVDD has the same type of sensitivity to data, interpolation rate, and the modulator function, but to a much lesser degree (< 10%).
Sleep/Power-Down Modes
The AD9861 provides multiple methods for programming power saving modes. The externally controlled TxPWRDWN or SPI programmed sleep mode and full power-down mode are the main options. TxPWRDWN is used to disable all clocks and much of the analog circuitry in the Tx path when asserted. In this mode, the biases remain active, therefore reducing the time required for re-enabling the Tx path. The time of recovery from powerdown for this mode is typically less than 10 s.
Latch/Demultiplexer
Data for the dual-channel Tx path can be latched in parallel through two ports in half-duplex operations (HD20 mode) or through a single port by interleaving the data (FD, HD10, and Clone modes). See the Flexible I/O Interface Options section in the Digital Block description and the Clock Distribution Block section for further descriptions of each mode.
Rev. 0 | Page 26 of 52
AD9861
AUXILIARY CONVERTERS
The AD9861 contains auxiliary analog-to-digital converters (AuxADCs) and auxiliary digital-to-analog converters (AuxDACs). These auxiliary converters can be used to measure or force system-wide control signals. By default, the auxiliary converters are disabled and powered down. Enabling and controlling the auxiliary converters is achieved through the serial programmable registers. Pins 29, 30, and 46 are configurable either as AuxDAC outputs or as AuxADC inputs. The respective AuxADC inputs are connected to the external pin when a conversion is initiated and are disconnected when the conversion is complete. The AuxDAC outputs are enabled by writing to the respective power-up registers in Register 0x29.
* * *
Update C, B, and A]. Slave mode is enabled by writing a high to the slave mode register bit [Register 0x28, Bit 7, Slave Enable]. Another synchronization mode allows any combination of AuxDACs to be updated along with an externally applied rising edge to the TxPwrDwn pin. Typical settling time for the AuxDAC output is less than 0.5 s, but is dependent on the load.
Auxiliary ADCs
Two auxiliary 10-bit SAR analog-to-digital converters (AuxADCs) are available for monitoring various external signals throughout the system, such as a receive signal strength indicator (RSSI) function or temperature indicator. The AuxADCs have many SPI programmable options. Register settings can be used to configure various full-scale reference options, change the sampling rate, and average multiple sample readings. By default, the AuxADC start conversion and output value is accessed through the register map. Additionally an auxiliary serial port can be enabled and used to initiate a conversion and read back the AuxADC data. The auxiliary serial port interface is available so that the normal SPI can be used to program other options while the AuxADC is accessed. By default, the AuxADCs are powered down and automatically powered up when a conversion is initiated. The two AuxADCs (AuxADC_A and AuxADC_B) can monitor up to three system signals. AuxADC_A has multiplexed inputs that control whether pin AUX_ADC_A1 or pin AUX_ADC_A2 is connected to the input of AuxADC_A. The multiplexer is programmed through Register 0x22, Bit 1, SelectA. By default, the register is low, which connects the AUX_ADC_A2 pin to the input. The full-scale AuxADC reference can be generated from the analog supply (supply dependent), an internal reference, or from an external applied reference. Table 10 shows the register settings required to select the AuxADC full-scale reference. By default, an internal reference provides a buffered full-scale reference for both of the AuxADCs, which is equal to the supply voltage for the AuxADCs (PLL_AVDD). A supply independent 2.5 V or 3.0 V internal full-scale reference can be enabled by writing to register AuxADC Ref Enable and AuxADC Ref FS in Register 0x17. This internal reference is based on the main Rx path ADC VREF voltage, so it requires the main Rx path VREF to be enabled. Another AuxADC full-scale reference option is an externally supplied full-scale reference. The external reference can be applied to either or both of the AuxADCs by setting the appropriate bit(s) in Registers 0x22 and 0x17. Setting either or both of these bits high disconnects the internal reference buffer and enables the externally applied reference from the AuxADC_Ref pin to the respective channel(s).
Pin 29 can be connected to AuxDAC_A and/or AuxADC_A Channel 2. Pin 30 can be connected to AuxDAC_B and/or AuxADC_A Channel 1. Pin 46 can be connected to AuxDAC_C and/or AuxADC_B.
Auxiliary DACs
The AD9861 integrates three 8-bit voltage output auxiliary digital-to-analog converters (AuxDACs), which can be used for supplying various control voltages throughout the system such as a VCXO voltage control or external VGA gain control. The AuxDACs have a programmable full-scale output voltage, VOUTFS, and can be synchronized to update with a single register write or a rising edge on the TxPwrDwn pin. By default, the AuxDAC outputs are powered down and require a serial write to the power-up registers [Register 0x29, Bits 2-0] to enable them. The full-scale output of each AuxDAC is independently programmable to the full scales of 2.5 V, 2.7 V, 3.0 V, or 3.3 V by using Serial Register 0x17. The AuxDAC outputs have an I-to-V driver that produces a voltage output that settles to 1 LSB within 0.5 s. The output driver is capable of sinking or sourcing up to 6 mA. Using the AuxDAC requires the SPI to be operational. The AuxDACs are based on a resistor divider network. The AuxDACs output level is proportional to the straight binary input codes from the appropriate SPI registers, Registers 0x24 to 0x26. By default, the AuxDAC output is updated immediately following the register write, but the update can occur synchronously to a single register write or to the TxPwrDwn rising edge. In slave mode, the AuxDAC update occurs when a logic high is written to the appropriate update registers [Register 0x28, Bits 2-0,
Rev. 0 | Page 27 of 52
AD9861
Table 10. Configuring AuxADC Reference
AuxADC_A Reference Configuration Buffered PLL_VDD Internal 3.0 V (3 x VREF) Internal 2.5 V (2.5 x VREF) Externally forced AuxADC Ref Enable [Register 0x17, Bit 1] 0 1 1 0 AuxADC Ref FS [Register 0x17, Bit 0] 0 0 1 Don't Care Refsel A/B [Register 0x22, Bit 2/Bit 5] 0 1 1 1
Notes Default mode. Decouple at AUXADC_REF pin. VREF voltage from Rx path. Decouple at AUXADC_REF pin. Force and decouple at AUXADC_REF pin.
The AuxADCs can convert at rates of up to 5.33 MSPS (0.1875 s maximum conversion time) and have a bandwidth of around 200 kHz. The conversion time, including setup, requires 12 clock cycles. The maximum clock rate for the AuxADCs is 64 MHz and is generated from a divided down Rx ADC clock. The divide down ratio is controlled by register AuxADC Clock Div [Register 0x23, Bits 1, 0]. By default, the Rx ADC clock is divided by 4. At an Rx ADC rate greater than 64 MHz, the AuxADC Clock Div register must be set to divide-by2 or divide-by-4. On-chip averaging of 2, 4, 8, 16, 32, or 64 samples can be enabled through Register 0x18 for AuxADC_A or through Register 0x19 for AuxADC_B. When the averaging option is enabled, the AuxADC continually converts the number of samples specified and outputs the average value. There are three modes of operating the AuxADC: SPI operation mode (default), SPI with external start convert operation mode, and Aux_SPI operation mode. In the default SPI operation mode, a conversion is initiated by writing a logic high to one or both of the start register bits, Start A or Start B [Register 0x22, Bit 0 or Bit 3]. If AuxADC is configured as averaging mode, the proper start bit is the Start Average AuxADC A/B register [Register 0x18, Bit 7/Register 0x19, Bit 7]. When the conversion is complete, the straight binary, 10-bit output data of the AuxADC is written to one of three reserved locations in the register map, depending on which AuxADC and which multiplexed input is selected. Because the AuxADCs output 10 bits, two register addresses are needed for each data location. In the optional SPI with external start convert operation mode, the conversion is initiated by asserting AuxSPI_csb, and data retrieval is accomplished through the SPI interface (data retrieval is similar to the default operation). The AuxSPI_csb can be configured to initiate the conversion of either one of the AuxADCs. This mode is configured by setting the AuxSPI enable register bit [Register 0x22, Bit 7]. An optional auxiliary serial port interface (AuxSPI) can be used to access an AuxADC. The AuxSPI can initiate an AuxADC conversion and can be used to retrieve the data. The AuxSPI can be configured to allow dedicated control of one of the
AuxADCs and is available so that the SPI is not continually busy retrieving AuxADC data. The AuxSPI can be enabled and configured by setting register AuxSPI enable [Register 0x22, Bit 7]. Also required is that the normal serial port interface be configured for 3-wire mode (the SPI_SDO pin must be disabled to use the Aux_SPI_SDO pin) by setting the SDIO BiDir register bit [Register 0x00, Bit 7]. Register bit Sel BnotA [Register 0x22, Bit 6] configures whether AuxADC_A or AuxADC_B is controlled by the AuxSPI. AuxADC_A has two inputs: AuxADC_A1 and AuxADC_A2. Setting the Select A bit [Register 0x22, Bit 1] determines which of the multiplexed inputs is connected to AuxADC_A. The AuxSPI consists of a chip select pin (AUX_SPI_CS, pin number 4), a clock pin (AUX_SPI_CLK), and a data output pin (AUX_SPI_SDO multiplex with the SPI_SDO pin). A conversion is initiated by pulsing the AUX_SPI_CS pin low (AUX_SPI_CS should remain low during the entire conversion cycle, including the readback phase). When the conversion is complete, the data pin, AUX_SPI_SDO, transitions from a logic low to a logic high. At this point, the user supplies an external clock on the AUX_SPI_CLK pin. The AUX_SPI_CLK pin should be tied low when not in use. No data is present on the first rising edge. The data output bit is updated on the falling edge of the clock pulse and is settled by and can be latched on the next clock rising edge. The data arrives serially, MSB first. The AuxSPI runs at a rate up to 16 MHz. Operation of the Aux_SPI requires that 3-wire SPI mode be used, disabling the SDO pin. If the controller is a 4-wire interface, a method of connecting the 3-wire AD9861 interface to the 4-wire controller is suggested in Figure 75. An example of an AuxSPI access is shown in Figure 75. In the AuxSPI configuration, a start convert is initiated by applying a rising edge to the Aux_SPI_CS pin. A rising edge on the Aux_SPI_DO pin indicates that a conversion is done. Supplying a clock to the Aux_SPI_CLK then outputs data on the Aux_SPI_DO pin, MSB first.
CONTROLLER SPI_CS[x] SPI_CLK SPI_DI
03606-0-006
AD986x SPI_CS SPI_CLK SPI_SDIO
Figure 75. Diagram to Connect 3-Wire SPI to a 4-Wire SPI Controller
Rev. 0 | Page 28 of 52
AD9861
Figure 76 shows a timing diagram of the AuxSPI when it is used to control and access an AuxADC. Figure 77 shows the timing for each of the three AuxADC modes of operation.
123
AUXSPI_CS AUXSPI_CLK AUXSPI_SDO D9 D8 1. AUXADC CONVERSION START SIGNAL 2. AUXADC CONVERSION DONE 3. AUXADC OUTPUT UDATE (MSB) D0
03606-0-021
Figure 76. Timing Diagram of AuxSPI
NORMAL SPI READOUT
16 SPI CLK 16 SPI CLKs USED TO CONFIGURE AND INITIATE A START CONVERSION
tCONVERSION = tC
16 SPI CLK
16 SPI CLKs USED TO READ BACK 8 REGISTER BITS
EXTERNAL START COVERT BIT AND SPI READOUT MODE
EXTERNAL PIN USED TO INITIATE A START CONVERSION 16 SPI CLKs USED TO READ BACK 8 REGISTER BITS
READOUT MODE WITH AUXILIARY SPI
EXTERNAL PIN USED TO INITIATE A START CONVERSION 8-BIT SERIAL OUTPUT
READOUT MODE WITH AUXILIARY SPI CYCLE TIME = tC + 8 SPI CLK EXTERNAL START COVERT BIT AND SPI READOUT MODE CYCLE TIME = tC + 16 SPI CLK NORMAL SPI READOUT CYCLE TIME = 16 SPI CLK + tC + 16 SPI CLK
03606-0-007
Figure 77. AuxADC Data Cycle Times for Various Readout Methods
Rev. 0 | Page 29 of 52
AD9861
DIGITAL BLOCK
The AD9861 digital block allows the device to be configured in various timing and operation modes. The following sections discuss the flexible I/O interfaces, the clock distribution block, and the programming of the device through mode pins or SPI registers.
Flexible I/O Interface Options
The AD9861 can accommodate various data interface transfer options (flexible I/O). The AD9861 uses two 10-bit buses, an upper bus (U10) and a lower bus (L10), to transfer the dualchannel 10-bit ADC data and dual-channel 10-bit DAC data by means of interleaved data, parallel data, or a mix of both. Table 11 shows the different I/O configurations of the modes depending on half-duplex or full-duplex operation. Table 12 and Table 13 summarize the pin configurations versus the modes.
Table 11. Flexible Data Interface Modes
Mode Name HD20 Tx Only Mode (Half-Duplex)
AD9861
U[0:9] L[0:9] IFACE1 IFACE2 IFACE3 Tx_A DATA Tx_B DATA Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-008
Rx Only Mode (Half-Duplex)
AD9861
L[0:9] Rx_A DATA Rx_B DATA Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-012
Concurrent Tx + Rx Mode (Full-Duplex)
General Notes
Rx Data Rate = 1 x ADC Sample Rate Two 10-Bit Parallel Rx Data Buses Tx Data Rate = 1 x ADC Sample Rate Two 10-Bit Parallel Tx Data Buses Rx Data Rate = 2 x ADC Sample Rate One 10-Bit Interleaved Rx Data Bus Tx Data Rate = 2 x ADC Sample Rate One 10-Bit Interleaved Tx Data Bus Rx Data Rate = 2 x ADC Sample Rate One 10-Bit Interleaved Rx Data Bus Tx Data Rate = 2 x ADC Sample Rate One 10-Bit Interleaved Tx Data Bus Rx Data Rate = 1 x ADC Sample Rate Two 10-Bit Parallel Rx Data Buses Tx Data Rate = 2 x ADC Sample Rate One 10-Bit Interleaved Tx Data Bus Requires SPI Interface to Configure; Similar to AD9860 Data Interface
DIGITAL BACK END
U[0:9] IFACE1 IFACE2 IFACE3
DIGITAL BACK END
N/A
HD10
AD9861
U[0:9] L[9] IFACE1 IFACE2 IFACE3 Tx_A/B DATA TxSYNC Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-009
AD9861
U[9] DIGITAL BACK END L[0:9] IFACE1 IFACE2 IFACE3 RxSYNC Rx_A/B DATA Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-013
DIGITAL BACK END
N/A
FD
AD9861
U[0:9] L[0:9] IFACE1 IFACE2 IFACE3 TxSYNC OUTPUT CLOCK OUTPUT CLOCK
03606-0-010
AD9861
Tx_A/B DATA DIGITAL BACK END U[0:9] L[0:9] IFACE1 IFACE2 IFACE3 OUTPUT CLOCK OUTPUT CLOCK
03606-0-014
AD9861
U[0:9] Rx_A/B DATA DIGITAL BACK END L[0:9] IFACE1 IFACE2 IFACE3 Tx_A/B DATA Rx_A/B DATA TxSYNC OUTPUT CLOCK OUTPUT CLOCK
03606-0-016
DIGITAL BACK END
Clone
AD9861
U[0:9] L[9] IFACE1 IFACE2 IFACE3 Tx_A/B DATA TxSYNC Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-011
AD9861
U[0:9] DIGITAL BACK END L[0:9] IFACE1 IFACE2 IFACE3 Rx_A DATA Rx_B DATA Tx/Rx OUTPUT CLOCK OUTPUT CLOCK
03606-0-015
DIGITAL BACK END
N/A
Rev. 0 | Page 30 of 52
AD9861
Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether transmitting or receiving.
Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases)
Mode Name FD HD10 (Tx/Rx = High) HD10 (Tx/Rx = Low) HD20 (Tx/Rx = High) HD20 (Tx/Rx = Low) Clone Mode (Tx/Rx = High) Clone Mode (Tx/Rx = Low) U10 Interleaved Tx Data Interleaved Tx Data MSB = RxSYNC Others = Three-state Tx_A Data Rx_B Data L10 Interleaved Rx Data MSB = TxSYNC Others = Three-state Interleaved Rx Data Tx_B Data Rx_A Data IFACE1 TxSYNC Tx/Rx = Tied High Tx/Rx = Tied Low Tx/Rx = Tied High Tx/Rx = Tied Low IFACE2 Buffered Rx Clock 10/20 Pin Control Tied High 10/20 Pin Control Tied High 10/20 Pin Control Tied Low 10/20 Pin Control Tied Low IFACE3 Buffered Tx Clock Buffered Tx Clock Buffered Rx Clock Buffered Tx Clock Buffered Rx Clock
Clone mode not available without SPI. Clone mode not available without SPI.
Table 13 describes AD9861 pin function (when SPI programming is used) relative to flexible I/O mode, and for half-duplex modes whether transmitting or receiving.
Table 13. AD9861 Pin Function vs. Interface Mode (Configured through the SPI Registers)
Mode Name FD HD10, Tx Mode (Tx/Rx = High) HD10, Rx Mode (Tx/Rx = Low) HD20, Tx Mode (Tx/Rx = High) HD20, Rx Mode (Tx/Rx = Low) Clone Mode , Tx Mode (Tx/Rx = High) Clone Mode , Rx Mode (Tx/Rx = Low) U10 Interleaved Tx Data Interleaved Tx Data MSB = RxSYNC Other = Three-state Tx_A Data Rx_B Data Interleaved Tx Data L10 Interleaved Rx Data MSB = TxSYNC Others = Three-state Interleaved Tx Data Tx_B Data Rx_A Data MSB = TxSYNC Others = Three-state Rx_A Data IFACE1 TxSYNC Tx/Rx = Tied High Tx/Rx = Tied Low Tx/Rx = Tied High Tx/Rx = Tied Low Tx/Rx = Tied High IFACE2 Buffered System Clock Optional Buffered System Clock Optional Buffered System Clock Optional Buffered System Clock Optional Buffered System Clock Optional Buffered System Clock Optional Buffered System Clock IFACE3 Buffered Tx Clock Buffered Tx Clock Buffered Rx Clock Buffered Tx Clock Buffered Rx Clock Buffered Tx Clock
Rx_B Data
Tx/Rx = Tied Low
Buffered Rx Clock
Summary of Flexible I/O Modes
FD Mode
The following notes provide a general description of the FD mode configuration. For more information, refer to Table 16. Note the following about the Tx path in FD mode:
* *
The full-duplex (FD) mode can be configured by using mode pins or with SPI programming. Using the SPI allows additional configuration flexibility of the device. FD mode is the only mode that supports full-duplex, receive, and transmit concurrent operation. The upper 10-bit bus (U10) is used to accept interleaved Tx data, and the lower 10-bit bus (L10) is used to output interleaved Rx data. Either the Rx path or the Tx path (or both) can be independently powered down using either (or both) the RxPwrDwn and TxPwrDwn pins. FD mode requires interpolation of 2x or 4x.
Interpolation rate of 2x or 4x can be programmed with mode pins or SPI. Max DAC update rate = 200 MSPS. Max Tx input data rate = 80 MSPS/channel (160 MSPS interleaved). TxSYNC is used to direct Tx input data. TxSYNC = high indicates channel Tx_A data. TxSYNC = low indicates channel Tx_B data.
*
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AD9861
*
Buffered Tx clock output (from IFACE3 pin) equals 2x the DAC update rate; one rising edge per interleaved Tx sample.
* * * *
Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS (AD9861-80). Output data rate = 2x ADC sample rate. Interleaved Rx data output from L10 bus. Rx_A output when IFACE2 (or RxSYNC) logic level = low. Rx_B output when IFACE2 (or RxSYNC) logic level = high.
Note the following about the Rx path in FD mode:
*
ADC CLK Div register can be used to divide down the clock driving the ADC, which accepts up to 50 MHz (AD9861-50) or up to 80 MHz (AD9861-80). Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS (AD9861-80). The Rx path output data rate is 2x the ADC sample rate (interleaved). Rx_A output when IFACE2 logic level = low. Rx_B output when IFACE2 logic level = high.
* * *
HD20 Mode
The half-duplex 20-bit parallel output, HD20, can be configured using mode pins or through SPI programming. HD20 mode supports half-duplex only operations and can interface to a single 20-bit data bus (two parallel 10-bit buses). Both the U10 and L10 buses are used on the AD9861. The logic level of the Tx/Rx selector (controlled through IFACE1 pin) is used to configure the buses as Rx outputs (during Rx operation) or as Tx inputs (during Tx operation). A single pin is used to output the clocks for Rx and Tx data latching (from the IFACE3 pin) switching, depending on which path is enabled. The following notes provide a general description of the HD20 mode configuration. For more information, refer to Table 16. Note the following about the Tx Path in HD20 mode:
* *
HD10 Mode
The half-duplex, 10-bit interleaved outputs mode, HD10 can be configured using mode pins or the SPI. HD10 mode supports half-duplex only operations and can interface to a single 10-bit data bus with independent Rx and Tx synchronization pins (RxSYNC and TxSYNC). Both the U10 and L10 buses are used on the AD9861, but the logic level of the Tx/Rx selector (controlled through IFACE1 pin) is used to disable and three-state the unused bus, allowing U10 and L10 to be tied together. The MSB of the unused bus acts as the RxSYNC (during Rx operation) or TxSYNC (during Tx operation). A single pin is used to output the clocks for Rx and Tx data latching (from the IFACE3 pin) switching, depending on which path is enabled. HD10 mode requires interpolation of 2x or 4x. The following notes provide a general description of the HD10 mode configuration. For more information, refer to Table 16. Note the following about the Tx path in HD10 mode:
* * *
Interpolation rate of 1x, 2x, or 4x can be programmed with mode pins or SPI. Max DAC update rate = 200 MSPS. Max Tx input data rate = 160 MSPS/channel with bypassed interpolation filters, 100 MSPS for 2x interpolation or 50 MSPS for 4x interpolation. Tx_A DAC data is accepted from the U10 bus; Tx_B DAC data is accepted from the L10 bus.
*
Interpolation rate of 2x or 4x can be programmed with mode pins or SPI. Interleaved Tx data accepted on U10 bus, L10 bus MSB acts as TxSYNC. Max DAC update rate = 200 MSPS. Max Tx input data rate = 80 MSPS/channel (160 MSPS interleaved). TxSYNC is used to direct Tx input data. TxSYNC = high indicates channel Tx_A data. TxSYNC = low indicates channel Tx_B data.
Note the following about the Rx path in HD20 mode:
*
ADC CLK Div register can be used to divide down the clock driving the ADC, which accepts up to 50 MHz (AD9861-50) or up to 80 MHz (AD9861-80). Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS (AD9861-80). The Rx_A output data is output on L10 bus; the Rx_B output data is output on U10 bus.
* *
*
Clone Mode
Note the following about the Rx path in HD10 mode:
*
ADC CLK Div register can be used to divide down the clock driving the ADC, which accepts up to 50 MHz (AD9861-50) or up to 80 MHz (AD9861-80).
An interface mode provides a similar interface to the AD9860 when used in half-duplex mode. This mode is referred to as clone mode and requires SPI to configure. Clone mode provides a parallel Rx data output (20 bits) while in Rx mode, and accepts interleaved Tx data (10-bit) while in Tx
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AD9861
mode. Both the U10 and L10 buses are used on the AD9861. The logic level of the Tx/Rx selector (controlled through the IFACE1 pin) is used to configure the buses for Rx outputs (during Rx operation) or as Tx inputs (during Tx operation). A single pin is used to output the clocks for Rx and Tx data latching (from the IFACE3 pin), depending on which path is enabled. Clone mode requires interpolation of 2x or 4x. The following notes provide a general description of the clone mode configuration. For more information, refer to Table 16. Note the following about the Tx path in clone mode:
* * * * *
Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS (AD9861-80). Output data rate = ADC sample rate, that is, two 10-bit parallel outputs per one buffer Rx clock output cycle. The Rx_A output data is output on L10 bus; the Rx_B output data is output on U10 bus.
Configuring with Mode Pins
The flexible interface can be configured with or without the SPI, although more options and flexibility are available when using the SPI to program the AD9861. Mode pins can be used to power down sections of the device, reduce overall power consumption, configure the flexible I/O interface, and program the interpolation setting. The SPI register map, which provides many more options, is discussed in the Configuring with SPI section.
Mode Pins/Power-Up Configuration Options
Interpolation rate of 2x or 4x can be programmed with mode pins or SPI. Max DAC update rate = 200 MSPS. Max Tx input data rate = 80 MSPS/channel (160 MSPS interleaved). TxSYNC is used to direct Tx input data. TxSYNC = high indicates channel Tx_A data. TxSYNC = low indicates channel Tx_B data. Buffered Tx clock output (from IFACE3 pin) uses one rising edge per interleaved Tx sample.
*
*
Note the following about the Rx path in clone mode:
*
Various options are configurable at power-up through mode pins, and also through control pins for power-down modes. The logic value of the configuration mode pins are latched when the device is brought out of reset (rising edge of RESET). The mode pin names and their functions are shown in Table 14. Table 15 provides a detailed description of the mode pins.
ADC CLK Div register can be used to divide down the clock driving the ADC, which accepts up to 50 MHz (AD9861-50) or up to 80 MHz (AD9851-80).
Duration Permanent Permanent Function When high, digital clocks to Rx block are disabled. Analog circuitry that require <10 s to power up are powered off. When high, digital clocks to Tx block are disabled (PLL remains powered to maintain output clock with an optional SPI shut off). Analog circuitry that require <10 s to power up are powered off. When high, digital clocks to Tx block are disabled (PLL remains powered to maintain output clock with an optional SPI shutoff). Tx analog blocks remain powered up unless Tx_PwrDwn is asserted. When low, digital clocks to Rx block are disabled. Rx analog circuitry remain powered up unless Rx_PwrDwn is asserted. When enabled, this bit scales the ADC power-down by 40%. This function is controlled through the SPI_CS pin. This pin must remain low to maintain mode pin functionality (the SPI port remains nonfunctional). This pin must be high when coming out of reset to enable the SPI. Configures the flex I/O for FD or HD mode. This control applies only if the SPI bus is disabled. If the flex I/O bus is in HD mode, this bit is used to configure parallel or interleaved data mode. This control applies only if the SPI bus is disabled. The Interp1 and Interp0 bits configure the PLL and the interpolation rate to 1x [00], 2x [01], or 4x [10]. This control applies only if the SPI bus is disabled.
Table 14. Mode Pin Names and Functions
Pin Name RxPwrDwn TxPwrDwn
Tx/Rx (IFACE1)
Permanent only for HD Flex I/O interface
ADC_LO_PWR SPI_Bus_Enable (SPI_CS) FD/HD 10/20 only valid for HD mode Interp0 and Interp1
Defined at Reset or Power-Up Defined at Reset or Power-Up Defined at Reset or Power-Up Defined at Reset or Power-Up Defined at Reset or Power-Up
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AD9861
Table 15. Mode Pin Names and Descriptions
Pin Name ADC_LO_PWR Description ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET. Logic low results in ADC operation at nominal power mode. Logic high results in ADC consuming 40% less power than the nominal power mode. For Flex I/O Configuration, this control applies only if the SPI bus is disabled. FD/HD (SDO) is latched during the rising edge of RESET. Logic low identifies that the DUT flex I/O port will be configured for half-duplex operation. 10/20 (IFACE2) is also latched during the rising edge of RESET to identify interleaved data mode or parallel data modes. Logic low indicates that the flex I/O will configure itself for parallel data mode. Logic high indicates that the flex I/O will configure itself for interleaved data mode. For flex I/O Configuration, The 10/20 pin control applies only if the SPI bus is disabled and the device is configured for HD mode. 10/20 is latched during the rising edge of RESET. 10/20 (IFACE2) is used to identify interleaved data mode or parallel data modes. Logic low indicates that the flex I/O will configure itself for HD20 mode. Logic high indicates that the flex I/O will configure itself for HD10 mode. SPI_CS is latched during the rising edge of RESET. Logic low results in the SPI being disabled and SPI_DIO, SPI_CLK and SPI_SDO act as mode pins. Logic high results in the SPI being fully operational, and some of the mode pins are disabled. Interpolation/PLL Factor Configuration. This control applies only if the SPI bus is disabled. SPI_DIO (Interp1) and SPI_CLK (Interp0) configure the Tx path for 1x [00], 2x [01], or 4x [10] interpolation and also enable the PLL of the same multiplication factor. Power-Down Control. RxPwrDwn logic level controls the power-down function of the Rx path. Logic low results in the Rx path operating at normal power levels. Logic high disables the ADC clock and disables some bias circuitry to reduce power consumption. Power-Down Control. TxPwrDwn logic level controls the power-down function of the Tx path. Logic low results in the Tx path operating at normal power levels. Logic high disables the DAC clocks and disables some bias circuitry to reduce power consumption. Power-Down Control. Tx/Rx pin enables the appropriate Tx or Rx path in the half-duplex mode. A logic low disables the Tx digital clock and the I/O bus is configured as an output or three-stated. A logic high disables the Rx digital clocks and the I/O bus is configured as high impedance inputs.
FD/HD (SDO)
10/ 20
SPI_Bus_Enable (SPI_CS)
Interp0 and Interp1
RxPwrDwn
TxPwrDwn
Tx/Rx
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AD9861
Configuring with SPI
The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 16 shows the required register writes to configure the AD9861 for FD, optional FD, HD20, optional HD20, HD10, optional HD10, and clone mode. Note that for modes that use interleaved data buses, enabling 2x or 4x interpolation is required.
Table 16. Registers for Configuring SPI
Register Address FD, Mode 1 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] Optional FD, Mode 2 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] HD20, Mode 4 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] Optional HD20, Mode 5 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] HD10, Mode 7 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] Optional HD10, Mode 8 Register 0x01 [7:5] Register 0x14 [4] Register 0x14 [2] Register 0x13 [1:0] Clone, Mode 10 Register 0x01 [7:5] Register 0x14 [0] Register 0x13 [1:0] Setting [000]; High High [01] or [10] [001] High High [01] or [10] [000]; Low Low [00], [01] or [10] [011] Low Low [00], [01] or [10] [000] Low High [01] or [10] [101] Low High [01] or [10] [111] High [01] or [10] Description clk_mode--Configures timing mode. SpiFDnHD--Configures FD mode. SpiB10n20--Configures FD mode. Interpolation Control--Configures 2x or 4x interpolation. clk_mode--Configures timing mode. SpiFDnHD--Configures FD mode. SpiB10n20--Configures FD mode. Interpolation Control--Configures 2x or 4x interpolation. clk_mode--Configures timing mode. SpiFDnHD--Configures HD mode. SpiB10n20--Configures HD20 mode. Interpolation Control--Configures 1x, 2x, or 4x interpolation. clk_mode--Configures timing mode. SpiFDnHD--Configures HD mode. SpiB10n20--Configures HD20 mode. Interpolation Control--Configures 1x, 2x, or 4x interpolation. clk_mode--Configures timing mode. SpiFDnHD--Configures HD mode. SpiB10n20--Configures HD10 mode. Interpolation Control--Configures 2x or 4x interpolation. clk_mode--Configures timing mode. SpiFDnHD--Configures HD mode. SpiB10n20--Configures HD10 mode. Interpolation Control--Configures 2x or 4x interpolation. clk_mode--Configures timing mode. SpiClone--Configures clone mode. Interpolation Control--Configures 2x or 4x interpolation.
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AD9861
SPI Register Map
Registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 18.
Table 17. Register Map
Reg. Name General Clock Mode Power-Down RxA Power-Down RxB Power-Down Rx Power-Down Rx Path Rx Path Rx Path Rx path Rx Path Tx Path Tx Path Tx Path Tx Path Tx Path Tx Path Tx Path Tx Path Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0B 0C 0D 0E 0F 10 11 12 DAC A Offset [9:2] DAC A Offset [1:0] DAC A Coarse Gain Control DAC B Offset [9:2] DAC B Offset [1:0] DAC B Coarse Gain Control TxPGA Gain [7:0] TxPGA Slave Enable Tx Twos Rx Twos Complement Complement PLL Bypass AuxDAC A FS [1:0] Start Average AuxADC A Start Average AuxADC B AuxADC A2 [1:0] AuxADC A2 [9:2] AuxADC A1 [1:0] AuxADC A1 [9:2] AuxADC B [1:0] AuxADC B [9:2] AuxSPI Enable AuxDAC A [7:0] AuxDAC B [7:0] AuxDAC C [7:0] Slave Enable AuxDAC C Sync TxPwrDwn DAC A Fine Gain [5:0] DAC B Offset Direction DAC B Fine Gain [5:0] TxPGA Fast Update Tx Inverse Sample Dig Loop On SpiFDnHD Alt Timing Mode ADC Clock Div PLL to IFACE2 AuxDAC B FS [1:0] Interpolation Control [1:0] SpiTxnRx PLL Div5 SpiB10n20 SPI IO Control SpiClone PLL Multiplier [2:0] PLL Slow AuxDAC C FS [1:0] AuxADC Ref AuxADC Ref Enable FS Number of AuxADC A Samples [2:0] Number of AuxADC B Samples [2:0] Rx Ultralow Power Control Rx Ultralow Power Control Rx Ultralow Power Control Rx Ultralow Power Control Rx Ultralow Power Control Rx Ultralow Power Control DAC A Offset Direction 7 SDIO BiDir clk_mode[2:0] Tx Analog Rx_A Analog Rx_B Analog Rx Analog Bias Rx_A DC Bias Rx_B DC Bias RxRef 6 LSB First 5 Soft Reset 4 3 2 Enable IFACE2 clkout PLL PowerDown 1 Inv clkout (IFACE3) PLL Output Disconnect 0
TxDigital
RxDigital
DiffRef Rx_A Twos Complement Rx_B Twos Complement
VREF Rx_A Clk Duty Rx_B Clk Duty Rx Ultralow Rx Ultralow Power Control Power Control
I/O Configuration 13 I/O Configuration Clock Clock Auxiliary Converters AuxADC AuxADC AuxADC AuxADC AuxADC AuxADC AuxADC AuxADC AuxADC AuxADC AuxDAC 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 22 23 24 25 26 28 29
Sel 2not1
Refsel B
Start B
Refsel A
Select A Start A AuxADC Clock Div[1:0]
AuxDAC B Sync TxPwrDwn
AuxDAC A Sync TxPwrDwn
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Update C Power-Up C
Update B Power-Up B
Update A Power-Up A
AD9861
Table 18. Register Bit Descriptions
Register Bit Register 0: General Bit 7: SDIO BiDir (Bidirectional) Description Default setting is low, which indicates that the SPI serial port uses dedicated input and output lines (4-wire interface), SDIO and SDO pins, respectively. Setting this bit high configures the serial port to use the SDIO pin as a bidirectional data pin. Default setting is low, which indicates MSB first SPI port access mode. Setting this bit high configures the SPI port access to LSB first mode. Writing a high to this register resets all the registers to their default values and forces the PLL to relock to the input clock. The soft reset bit is a one-shot register, and is cleared immediately after the register write is completed. These bits represent the clocking interface for the various modes. Setting 000 is default. Setting 111 is used for clone mode. Refer to the Summary of Flexible I/O Modes section for definition of clone mode. Setting Mode 000 Standard FD, HD10, HD20 Clock (Modes 1, 4, 7) 001 Optional FD timing (Mode 2) 010 Not Used 011 Optional HD20 timing (Mode 5) 100 Not Used 101 Optional HD10 timing (Mode 8) 110 Not Used 111 Clone Mode (Mode 10) Enables the IFACE2 port to be an output clock. Also inverts the IFACE2 output clock in full-duplex mode. Invert the output clock on IFACE3. Three options are available to reduce analog power consumption for the Tx channels. The first two options disable the analog output from Tx Channel A or B independently, and the third option disables the output of both channels and reduces the power consumption of some of the additional analog support circuitry for maximum power savings. With all three options, the DAC bias current is not powered down so recovery times are fast (typically a few clock cycles). The list below explains the different modes and settings used to configure them. Power-Down Option Bits Setting [7:5] Power-Down Tx A Channel Analog Output [1 0 0] Power-Down Tx B Channel Analog Output [0 1 0] Power-Down Tx A and Tx B Analog Outputs [1 1 1] Default setting is low, which enables the transmit path digital to operate as programmed through other registers. By setting this bit high, the digital blocks are not clocked to reduce power consumption. When enabled, the Tx outputs are static, holding their last update values. Setting this bit high powers down the digital section of the receive path of the chip. Typically, any unused digital blocks are automatically powered down. Setting this register bit high forces the CLKIN multiplier to a power-down state. This mode can be used to conserve power or to bypass the internal PLL. To operate the AD9861 when the PLL is bypassed, an external clock equal to the fastest on-chip clock is supplied to the CLKIN. Setting this register bit high disconnects the PLL output from the clock path. If the PLL is enabled, it locks or stays locked as normal. Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The entire analog circuitry of Rx channel is powered down, including the differential references, input buffer, and the internal digital block. The band gap reference remains active for quick recovery. Setting either of these bits high powers down the input common-mode bias network for the respective channel and requires an input signal to be properly dc-biased. By default, these bits are low, and the Rx inputs are self-biased to approximately AVDD/2 and accept an ac-coupled input. Setting this bit high powers down all analog bias circuits related to the receive path (including the differential reference buffer). Because bias circuits are powered down, an additional power saving, but also a longer recovery time relative to other Rx power-down options, will result.
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Bit 6: LSB First Bit 5: Soft Reset
Register 1: Clock Mode Bits 7-5: Clk Mode
Bit 2: Enable IFACE2 clkout Bit 1: Inv clkout (IFACE3) Register 2: Power-Down Bits 7-5: Tx Analog (PowerDown)
Bit 4: Tx Digital (Power-Down)
Bit 3: Rx Digital (Power-Down) Bit 2: PLL Power-Down
Bit 1: PLL Output Disconnect Register 3/4: Rx Power-Down Bit 7: Rx_A Analog/ Rx_B Analog (Power-Down) Bit 6: Rx_A DC Bias/ Rx_B DC Bias (Power-Down) Register 5: Rx Power-Down Bit 7: Rx Analog Bias (PowerDown)
AD9861
Register Bit Bit 6: RxREF (Power-Down) Description Setting this register bit high powers down internal ADC reference circuits. Powering down these circuits provides additional power saving over other power-down modes. The Rx path wake-up time depends on the recovery of these references typically of the order of a few milliseconds. Setting this bit high powers down the ADC's differential references, REFT and REFB. Recovery time depends on the value of the REFT and REFB decoupling capacitors. Setting this register bit high powers down the ADC reference circuit, VREF. Powering down the Rx band gap reference allows an external reference to drive the VREF pin setting full-scale range of the Rx paths. Default data format for the Rx data is straight binary. Setting this bit high generates twos complement data. Setting either of these bits high enables the respective channels on-chip duty cycle stabilizer (DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for high speed input clocks with skewed duty cycle. The DCS mode can be used with ADC sampling frequencies over 40 MHz. Set all bits high, in combination with asserting the ADC_LO_PWR pin, to reduce the power consumption of the Rx path by a fourth of normal Rx path power consumption. These 10-bit, twos complement registers control a dc current offset that is combined with the Tx A or Tx B output signal. An offset current of up to 12% IOUTFS (2.4 mA for a 20 mA full-scale output) can be applied to either differential pin on each channel. The offset current can be used to compensate for offsets that are present in an external mixer stage, reducing LO leakage at its output. The default setting is 0x00, no offset current. The offset current magnitude is set by using the lower nine bits. Setting the MSB high adds the offset current to the selected differential pin, while an MSB low setting subtracts the offset value. This bit determines to which of the differential output pins for the selected channel the offset current is applied. Setting this bit low applies the offset to the negative differential pin. Setting this bit high applies the offset to the positive differential pin. These register bits scale the full-scale output current (IOUTFS) of either Tx channel independently. IOUT of the Tx channels is a function of the RSET resistor, the TxPGA setting, and the coarse gain control setting. 00 Output current scaling by 1/11 01 Output current scaling by 1/2 10 No output current scaling 11 No output current scaling The DAC output curve can be adjusted fractionally through the gain trim control. Gain trim of up to 4% can be achieved on each channel individually. The gain trim register bits are a twos complement attention control word. 100000 Maximum positive gain adjustment 111111 Minimum positive gain adjustment 000000 No adjustment (default) 000001 Minimum negative gain adjustment 011111 Maximum negative gain adjustment This 8-bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) register controls for the Tx programmable gain amplifier (TxPGA). The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear in dB) simultaneously to both Tx channels. By default, this register setting is 0xFF. 0000 0000 Minimum gain scaling -20 dB 1111 1111 Maximum gain scaling 0 dB The TxPGA gain is controlled through register TxPGA gain setting and, by default, is updated immediately after the register write. If this bit is set, the TxPGA gain update is synchronized with the falling edge of a signal applied to the TxPwrDwn pin and is enabled during the wake-up from power-down.
Bit 5: DiffRef (Power-Down) Bit 4: VREF (Power-Down)
Registers 6/7: Rx Path Bit 5: Rx_A Twos Complement/ Rx_B Twos Complement Bit 4: Rx_A Clk Duty/Rx_B Clk Duty
Registers 8/9/A: Rx Path Rx Ultralow Power Control Bits Registers 0B/0C/0E/0F: Tx Path DAC A/DAC B Offset
DAC A/DAC B Offset Direction
Registers 0D/10: Tx Path Bits 7, 6: DAC A/DAC B Coarse Gain Control
Bits 5-0: DAC A/DAC B Fine Gain
MSB, LSB
Register 11: Tx Path Bits 0-7: TxPGA Gain
MSB, LSB Register 12: Tx Path Bit 6: TxPGA Slave Enable
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AD9861
Register Bit Bit 4: TxPGA Fast Update (Mode) Description The TxPGA fast bit controls the update speed of the TxPGA. When fast update mode is enabled, the TxPGA provides fast gain settling within a few clock cycles, which may introduce spurious signals at the output of the Tx path. The default setting for this bit is low, and the TxPGA gives a smooth transition between gain settings. Fast mode is enabled when this bit is set high. The default data format for Tx data is straight binary. Set this bit high when providing twos complement Tx data. The default data format for Rx data is straight binary. Set this bit high when providing twos complement Rx data. By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high changes this, and the transmit data is sampled on the falling edge. These register bits control the interpolation rate of the transmit path. The default settings are both bits low, indicating that both interpolation filters are bypassed. The MSB and LSB are Address Bits 1 and 0, respectively. Setting binary 01 provides an interpolation rate of 2x; binary 10 provides an interpolation rate of 4x. When enabled, this bit enables a digital loop back mode. The digital loop-back mode provides a means of testing digital interfaces and functionality at the system level. In digital loop-back mode, the full-duplex interface must be enabled. (Refer to the Flexible I/O Interface Options section.) The device accepts digital input from the bus according to the FD mode timing and uses the Tx digital path (with enabled interpolation and other digital settings); the processed data is then output from the Rx path bus. Control bit to configure full-duplex (high) or half-duplex (low) interface mode. This register, in combination with the SpiB10n20 register, configures the interface mode of FD, HD10, or HD20. The register setting is ignored for clone mode operation. By default, this register is set high, and the device is in FD mode. Control bit used for toggling between transmit or receive mode for the half-duplex clock modes. High represents Tx and low represents Rx. Control bit for 10-bit or 20-bit modes. High represents 10-bit mode and Low represents 20-bit mode. Use in conjunction with SpiTxnRx [Register14, Bit 3] to override external TxnRx pin operation. Set high when in clone mode (see the Flexible I/O Interface Options section for definition of clone mode). Clk_mode should also be set to binary 111, i.e., [Register 01[7:5] = 111. Setting this bit high bypasses the PLL. When bypassed, the PLL remains active. By default, the ADCs are driven directly from CLKIN in normal timing operation or from the PLL output clock in the alternative timing operation. This bit is used to divide the source of the ADC clock prior to the ADCs. The default setting is low and performs no division. Setting this bit high divides the clock by 2. The timing table in the data sheet describes two timing modes: the normal timing operation mode and the alternative timing operation mode. The default configuration is normal timing mode and the CLKIN drives the Rx path. In alternative timing mode, the PLL output is used to drive the Rx path. The alternative operation mode is configured by setting this bit high. The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives the Tx digital path with no division of its output. These bits control the PLL multiplication factor. A default setting is binary 000, which configures the PLL to 1x multiplication factor. This register, in combination with the PLL Div5 register, sets the PLL output frequency. The programmable multiplication factors are 000 1x 001 2x 010 4x 011 8x 100 16x 101 - 111 not used Setting this bit high switches the IFACE2 output signal to the PLL output clock. It is valid only if Register 0x01, Bit 2 is enabled or if full-duplex mode is configured. Changes the PLL loop bandwidth and changes the profile of the phase noise generated from the PLL clock.
Rev. 0 | Page 39 of 52
Register 13: I/O Configuration Bit 7: Tx Twos Complement Bit 6: Rx Twos Complement Bit 5: Tx Inverse Sample Bits 1,0: Interpolation Control
Register 14: I/O Configuration Bit 5: Dig Loop On
Bit 4: SPI_FDnHD
Bit 3: SpiTxnRx Bit 2: SpiB10n20 Bit 1: SPI IO Control Bit 0: SpiClone Register 15: Clock Bit 7: PLL_Bypass Bits 5: ADC Clock Div
Bit 4: Alt Timing Mode
Bit 3: PLL Div5 Bits 2-0: PLL Multiplier
Register 16: Clock Bit 5: PLL to IFACE2 Bit 2: PLL Slow
AD9861
Register Bit Register 17: Auxiliary Converters Bits 7-2: AuxDAC A FS/AuxDAC B FS/AuxDAC C FS Description These register bits independently scale the full-scale output voltage for the AuxDACs. If the fullscale voltage is programmed to a value greater than PLL_VDD - 0.2 V, the AuxDAC becomes nonlinear in this region. MSB, LSB AuxDAC Full-Scale Output Voltage 00 3.0 V 01 3.3 V 10 2.5 V 11 2.7 V This bit enables the on-chip, supply independent reference for the AuxADC. By default, the AuxADC uses the PLL_AVDD supply for its full-scale voltage level. When the AuxADC Ref Enable bit is set high, this bit allows the user to select the full-scale value of the AuxADC. A low setting sets the full-scale value to 3.0 V; a high setting sets the full-scale value to 2.5 V. If the full-scale voltage is programmed to a value greater than PLL_VDD - 0.2 V, the AuxADC is not linear in this region. These registers are used to initiate a conversion cycle of the AuxADCs for a number of consecutive samples and then report the average result. The number of consecutive samples is programmed in the number of AuxADC A/AuxADCB samples register. The external pin Aux_SPI_CS can be configured to allow it to initiate the start average conversion cycle. The result is placed in the appropriate register corresponding to the AuxADC output [Registers 0x1A to 0x21]. These bits control the number of samples that the AuxADC collects and uses to calculate an average value. This register is used in conjunction with the start average AuxADC register. MSB, LSB Number of Samples to Average 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 Not Used These 10-bit, offset binary registers are read-only and store the last corresponding AuxADC output values. The AD9861 has two AuxADC SAR converters: AuxADC A and AuxADC B. AuxADC A has a multiplexed input, which allows the user to select either input by using the Select A register. The 10 bits are broken into two registers, one containing the upper eight bits and the other containing the lower two bits. Enables the AuxSPI, which can be used to initiate a conversion and read back one of the AuxADCs. If the auxiliary serial port is used, this bit selects which AuxADC, 1 or 2, uses the dedicated auxiliary serial port. By default (low setting), the auxiliary serial port controls AuxADC A. Setting this bit high allows the auxiliary serial port to control AuxADC B. By default, the AuxADCs use an external reference applied to the AUX_REF pin. This voltage acts as the full-scale reference for the selected AuxADC. Either AuxADC can use an internally generated reference, which can be a buffered version of the analog supply voltage or a supply independent, 3.0 V or 2.5 V internal reference. To enable use of the internal reference for either of the AuxADCs, set the respective Refsel register high. For internal reference configuration, see Register 17. This bit is used to select which of the two inputs is connected to the AuxADC. By default (setting low), the AUX_ADC_A2 (Aux2 pin) is connected to AuxADC A. Setting the respective bit high connects the AUX_ADC_A1 (Aux1 pin) to AuxADC A. Setting either of these bits to high initiates a conversion of the respective AuxADC, A or B. The register bit always reads back a low.
Bit 1: AuxADC Ref Enable Bit 0: AuxADC Ref FS
Registers 18/19 : AuxADC Bit 7: Start Average AuxADC A/ Start Average AuxADC B
Bit 7: Number of AuxADC A/ AuxADC B Samples
Registers 1A-21: AuxADC
Register 22: AuxADC Bit 7: AuxSPI (Enable) Bit 6: Sel 2not1
Bits 5, 2: Refsel B/A
Bit 1: Select A
Bit 3, 0: Start B/A
Rev. 0 | Page 40 of 52
AD9861
Register Bit Register 23: AuxADC Bits 1,0: AuxADC Clock Div Description The AuxADCs clock can be based on either the clock driving the Rx ADC, or it can be driven from the SPI_CLK. The conversion rate of the AuxADCs should be less than 40 MHz. In order to facilitate a slower speed clock for the AuxADC, these bits are used to divide down the Rx ADC clock prior to driving the AuxADC. The following options are programmable through this register: MSB, LSB AuxADC Sampling Rate 00 Rx ADC Clock/4 01 Rx ADC Clock/2 10 Rx ADC Clock 11 SPI_CLK drives AuxADC Three 8-bit, straight binary words are used to control the output of three on-chip AuxDACs. The AuxDAC output changes take effect immediately after any of the serial writes are completed. The DAC output control words have default values of 0. The smaller programmed output controlled words correspond to lower DAC output levels. A low setting (default) updates the AuxDACs after the respective register is written to. To synchronize the AuxDAC outputs to each other, a slave mode can be enabled by setting this bit high and then setting the appropriate update registers high. Setting a high bit to any of these bits initiates an update of the respective AuxDAC, A, B or C, when slave mode is enabled using the slave enable register. The register bit is a one-shot and always reads back a low. Be sure to keep the slave enable bit high when using the AuxDAC synchronization option. Setting any of these bits high synchronizes AuxDAC updates only when the TxPwrDwn rising edge occurs. This syncronizes the AuxDAC update to the Tx path power-up. Setting any of these bits high powers up the appropriate AuxDAC. By default, these bits are low and the AuxDACs are disabled.
Registers 24, 25, 26: AuxDAC AuxDAC A, B, and C Output Control Word
Register 28: AuxDAC Bit 7: Slave Enable
Bits 2/1/0: Update C, B, and A
Register 29: AuxDAC Bits 7/6/5: AuxDAC C/B/A Sync TxPwrDwn Bits 2/1/0: Power Up C, B, and A
Rev. 0 | Page 41 of 52
AD9861
PROGRAMMABLE REGISTERS
The AD9861 contains internal registers that are used to configure the device. A serial port interface provides read/write access to the internal registers. Single-byte or dual-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9861's serial interface port can be configured as a single pin I/O (SDIO) or as two unidirectional pins for in/out (SDIO/SDO). The serial port is a flexible, serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. cycle. Phase 2 is the actual data transfer between the AD9861 and the system controller. Phase 2 of the communication cycle is a transfer of one or two data bytes as determined by the instruction byte. Normally, using one communication cycle in a multibyte transfer is the preferred method; however, single byte communication cycles are useful to reduce CPU overhead when register access requires only one byte. An example of this is to write the AD9861 power-down bits. All data input to the AD9861 is registered on the rising edge of SCLK. All data is driven out of the AD9861 on the falling edge of SCLK.
Instruction Byte
General Operation of the Serial Interface
By default, the serial port accepts data in MSB first mode and uses four pins: SEN, SCLK, SDIO, and SDO by default. SEN is a serial clock enable pin; SCLK is the serial clock pin; SDIO is a bidirectional data line; and SDO is a serial output pin. SEN is an active low control gating read and write cycles. When SEN is high, SDO and SDIO go into a high impedance state. SCLK is used to synchronize SPI read and writes at a maximum bit rate of 30 MHz. Input data is registered on the rising edge, and output data transitions are registered on the falling edge. During write operations, the registers are updated after the 16th rising clock edge (and 24th rising clock edge for the dual-byte case). Incomplete write operations are ignored. SDIO is an input data only pin by default. Optionally, a 3-pin interface may be configured using the SDIO for both input and output operations and three-stating the SDO pin. Refer to the SDIO BiDir bit in Register 0x00 (Table 18).
SDO is a serial output data pin used for readback operations in
The instruction byte contains the information shown in Table 19, and the bits are described in detail after the table.
Table 19. Instruction Byte
MSB R/nW D6 2/n1 Byte D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 LSB A0
R/nW--Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic high indicates a read operation. Logic low indicates a write operation. 2/n1 Byte--Bit 6 of the instruction byte determines the number of bytes to be transferred during the data transfer cycle of the communication cycle. Logic high indicates a 2-byte transfer. Logic low indicates a 1-byte transfer. A5, A4, A3, A2, A1, A0--Bits 5, 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communication cycle. For 2-byte transfers, this address is the starting byte address. The second byte address is automatically decremented when the interface is configured for MSB first transfers. For LSB first transfers, the address of the second byte is automatically incremented. Table 20. Serial Port Interface Timing
Maximum SCLK Frequency (fSCLK) Minimum SCLK High Pulse Width (tPWH) Minimum SCLK Low Pulse Width (tPWL) Maximum Clock Rise/Fall Time Data to SCLK timing (tDS) Data Hold Time (tDH) 40 MHz 12.5 ns 12.5 ns 1 ms 12.5 ns 0 ns
4-wire mode and is three-stated when SDIO is configured for bidirectional operation. There are two phases to a communication cycle with the AD9861. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9861, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9861 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (one or two), and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9861. The remaining SCLK edges are for Phase 2 of the communication
Rev. 0 | Page 42 of 52
AD9861
Write Operations
The SPI write operation uses the instruction header to configure a 1-byte or 2-byte register write using the 2/n1 byte setting. The instruction byte followed by the register data is written serially into the device through the SDIO pin on rising edges of the interface clock, SCLK. The data can be transferred MSB first or LSB first depending on the setting of the LSB first register bit. The write operation is the same regardless of SDIO BiDir register setting.
Figure 78 to Figure 80 are examples of writing data into the device. Figure 78 shows a 1-byte write with MSB first; Figure 79 shows a 2-byte write with MSB first; and Figure 80 shows a 2-byte write with LSB first. Note the differences between LSB and MSB first modes: both the instruction header and data are reversed, and the second data byte register location is different. In the default MSB first mode, the second data byte is written to a decremented register address. In LSB first mode, the second data byte is written to an incremented register address.
tDS tS
SEN
tHI tDH tLO
tCLK
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
2/1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
03606-0-022
INSTRUCTION HEADER
REGISTER DATA
Figure 78. 1-Byte Serial Register Write in MSB First Mode
tS tDH tDS
tHI tLO tCLK
tH
SEN
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
2/1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0 D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
INSTRUCTION HEADER (REGISTER N)
REGISTER (N) DATA
REGISTER (N-1) DATA
03606-0-023
Figure 79. 2-Byte Serial Register Write in MSB First Mode
tS
SEN
tDS tDH
tLO
tHI tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
A0
A1
A2
A3
A4
A5
2/1 R/W D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
DON'T CARE
INSTRUCTION HEADER (REGISTER N)
REGISTER (N) DATA
REGISTER (N+1) DATA
03606-0-024
Figure 80. 2-Byte Serial Register Write in LSB First Mode
Rev. 0 | Page 43 of 52
AD9861
Read Operation
The readback of registers can be a single or dual data byte operation. The readback can be configured to use 3-wire or 4-wire and can be formatted with MSB first or LSB first. The instruction header is written to the device either MSB or LSB first (depending on the mode) followed by the 8-bit output data (appropriately MSB or LSB justified). By default, the output data is sent to the dedicated output pin (SDO). Three-wire operation
tHI tLO
can be configured by setting the SDIO BiDir register. In 3-wire mode, the SDIO pin becomes an output pin after receiving the 8-bit instruction header with a readback request. Figure 81 shows a 4-wire SPI read with MSB first; Figure 82 shows a 3-wire read with MSB first; and Figure 83 shows a 4-wire read with LSB first.
tS
tDS tDH
tCLK tDV
tH
SEN SCLK DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
2/1
A5
A4
A3
A2
A1
A0
DON'T CARE
INSTRUCTION HEADER SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
03606-0-025
OUTPUT REGISTER DATA
Figure 81. 1-Byte Serial Register Readback In MSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)
tS
SEN
tDS tDH
tHI tLO
tCLK tDV
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
2/1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
03606-0-026
INSTRUCTION HEADER
OUTPUT REGISTER DATA
Figure 82. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic High (Default, 3-Wire Mode)
tS
SEN
tDS tDH
tHI tLO
tCLK tDV
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
DON'T CARE
A0
A1
A2
A3
A4
A5
2/1
R/W
DON'T CARE
INSTRUCTION HEADER SDO DON'T CARE D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE
03606-0-027
OUTPUT REGISTER DATA
Figure 83. 1-Byte Serial Register Readback in LSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)
Rev. 0 | Page 44 of 52
AD9861
CLOCK DISTRIBUTION BLOCK
Theory/Description
The AD9861 uses a clock distribution block to distribute the timing derived from the input clock (applied to the CLKIN pin, referred to here as CLKIN) to the Rx and Tx paths. There are many options for configuring the clock distribution block, which are available through internal register settings. The Clock Distribution Block Diagram section describes the timing block diagram breakdown, followed by the data timing for the different data interface options. The clock distribution block contains a PLL, which includes an optional output divide-by-5 circuit, an ADC divide-by-2 circuit, multiplexers, and other digital logic. There are two main methods of configuring the Rx path timing of the AD9861, normal timing mode and alternative timing mode, which are controlled through register Alt timing mode [Register 0x15, Bit 4]. In normal timing mode, the Rx path clock is driven directly from the CLKIN input and the Tx path is driven by a clock derived from CLKIN multiplied by the on chip PLL. In alternative timing mode, the input clock is applied to the PLL circuitry, and the PLL output clock drives both the Rx path clock and Tx path clock. Because alternative timing mode uses the PLL to derive the Rx path clock, the ADC performance may degrade slightly. This degradation is due to the phase noise from the PLL. Typically it occurs in undersampling applications when the input signal is above the first Nyquist zone of the ADC. The PLL can provide 1x, 2x, 4x, 8x, and 16x multiplication or can be bypassed and powered down through register PLL bypass [Register 0x15, Bit 7] and through register PLL powerdown [Register 0x2, Bit 2]. The PLL requires a minimum input clock frequency of 16 MHz and needs to provide a minimum PLL output clock of 32 MHz. This limit applies to the PLL output prior to the optional divide-by-5 circuitry. For clock frequencies below these limits, the PLL must be bypassed. The PLL maximum output frequency before the divide-by-5 circuitry is 350 MHz. Table 21 shows the input and output clock rates for all the multiplication settings.
Table 21. PLL Input and Output Minimum and Maximum Clock Rates
PLL Setting 1x (PLL Bypassed) 1x (PLL Enabled) 2x 4x 8x * 1/5 x * 2/5 x * 4/5 x * 8/5 x * 16/5 x Input Clock (Min/Max) (MHz) 1/200 32/200 16/100 16/50 16/25 32/200 16/175 16/87.5 16/43.75 16/21.875 Output Clock (Min/Max) (MHz) 1/200 32/200 32/200 64/200 128/200 6.4/40 6.4/70 12.8/70 25.6/70 51.2/70
* Indicates PLL output divide-by-5 circuit enabled.
Clock Distribution Block Diagram
The Clock Distribution Block diagram is shown in Figure 84. An output clock formatter configures the output synchronization signals, IFACE1, IFACE2, and IFACE3. These interface pin signals depend on clock mode setting, data I/O configuration, and other operational settings. Clock mode and data I/O configuration are defined in register settings of clk_mode, SpiFDnHD, and SpiB10n20. Table 22 shows the configuration of the IFACE1, IFACE2 and IFACE3 pins relative to clock mode (for half-duplex cases, the IFACE1 pin is an input that identifies if the device is in Rx or Tx operation mode). The clock mode is used to specify the timing for each data interface operation modes, which are discussed in detail in the Flexible I/O Interface Options section. The T and R extensions after the half-duplex Modes 4, 5, 7, 8, and 10 in the Table 22 indicate that the device is in transmit or receive operation mode. The default clock mode setting [Register 0x01, Bits 5-7, clk_mode] of `000' configures clock Mode 1 for the full-duplex operation, Mode 4 for half-duplex 20 operation and Mode 7 for half-duplex 10 operation. Modes 2, 5, 8, and 10 are optional timing configurations for the AD9861 that can be programmed through Register 0x01 clk_mode.
Rev. 0 | Page 45 of 52
AD9861
80MHz MAX CLKIN 1, 2 Rx DIGITAL BLOCK Rx PATH IFACE2 OUTPUT CLOCK FORMATTER Tx PATH IFACE3
1
4
1, 2, 4, 8, 16
1, 5 Tx DIGITAL BLOCK 5
3
6 2
1. ALTERNATE TIMING MODE: REG 0x15, BIT 4 2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2-0 3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT 3 4. Rx PATH DIVIDE BY 2: REG 0x15, BIT 5 5. PLL BYPASS PATH: REG 0x15, BIT 7 6. INTERP CONTROL, Tx/Rx INV IFACE3, CLK MODE, INV IFACE2, FD/HD, 10/20
Figure 84. Clock Distribution Block Diagram
Table 22. Interface Pins (IFACE1, IFACE2, IFACE3) Configuration Definition for Flexible Interface Operation
Clock Mode PIN IFACE1 IFACE2 IFACE3 1 Full-Duplex TxSync Buff_CLKIN Tx Clock RxSync 2 4T 4R 5T 5R 7T 7R 8T 8R 10T 10R
Half-Duplex, 20-Bit Tx/Rx Optional CLKOUT Tx Rx Tx Clock Clock Clock
Rx Clock
Half-Duplex, 10-Bit Tx/Rx Optional CLKOUT Tx Rx Tx Clock Clock Clock
03606-0-067
Rx Clock
Clone Mode Tx/Rx Optional CLKOUT Tx Rx Clock Clock
The Tx clock output frequency depends on whether the data is in interleaved or parallel (noninterleaved) configuration. Modes 1, 2, 7, 8, and 10 use Tx interleaved data and require either 2x or 4x interpolation to be enabled.
* * *
DAC update rate = CLKIN x PLL setting. Noninterleaved Tx data clock frequency = CLKIN x PLL setting x 1/(interpolation rate). Interleaved Tx data clock frequency = 2 x CLKIN x PLL setting x 1/(interpolation rate).
An optional CLKOUT from IFACE2 is available as a stable system clock running at the CLKIN frequency or the TxDAC update rate, which is equal to CLKIN x PLL setting. Setting the enable IFACE2 register [Register 0x01, Bit 2] enables the IFACE2 optional clock output. In FD mode, the IFACE2 pin always acts as a clock output; the enable IFACE2 pin can be used to invert the IFACE2 output.
Configuration
The AD9861 timing for the transmit path and for the receive path depend on the mode setting and various programmable options. The registers that affect the output clock timing and data input/output timing are clk_mode [2:0]; enable IFACE2; inv clkout (IFACE3); Tx inverse sample; interpolation control; PLL bypass; ADC clock div; Alt timing mode; PLL Div5; PLL multiplication; and PLL to IFACE2. The clk_mode register is discussed previously. Table 23 shows the other register bits that are used to configure the output clock timing and data latching options available in the AD9861.
The Rx clock does not depend on whether the data is interleaved or parallel, but does depend on the configuration of the timing mode: normal or alternative.
* *
Normal timing mode, Rx clock frequency = CLKIN x ADC Div factor (if enabled). Alternative timing mode, Rx clock frequency = CLKIN x PLL setting x ADC Div factor (if enabled).
Rev. 0 | Page 46 of 52
AD9861
Table 23. Serial Registers Related to the Clock Distribution Block
Register Name Enable IFACE2 Register Address, Bit(s) Register 0x01, Bit 2 Function 0: There is no clock output from IFACE2 pin, except in FD mode. 1: The IFACE2 pin outputs a continuous reference clock from the PLL output. In FD mode, this inverts the IFACE2 output. 0: The IFACE3 clock output is not inverted. 1: The IFACE3 clock output is inverted. 0: The Tx path data is latched relative to the output Tx clock rising edge. 1: The Tx path data is latched relative to the output Tx clock falling edge. Sets interpolation of 1x, 2x, or 4x for the Tx path. 0: The PLL block is used to generate system clock. 1: The PLL block is bypassed to generate system clock. 0: ADC clock rate equals the Rx path frequency. 1: ADC clock is one-half the Rx path frequency. 0: CLKIN is used to drive the Rx path clock. 1: PLL block output is used to drive the Rx path clock. 0: PLL block output clock is not divided down. 1: PLL block output clock is divided by 5. Sets multiplication factor of the PLL block to 1x (000), 2x (001), 4x (010), 8x (011), or 16x (100). 0: If enable IFACE2 register is set, IFACE2 outputs buffered CLKIN. 1: If enable IFACE2 register is set, IFACE2 outputs buffered PLL output clock.
Inv clkout (IFACE3) Tx Inverse Sample Interpolation Control PLL Bypass ADC Clock Div Alt Timing Mode PLL Div5 PLL Multiplier PLL to IFACE2
Register 0x01, Bit 1 Register 0x13, Bit 5 Register 0x13, Bit 1:0 Register 0x15, Bit 7 Register 0x15, Bit 5 Register 0x15, Bit 4 Register 0x15, Bit 3 Register 0x15, Bit 2:0 Register 0x16, Bit 5
Transmit (Tx) timing requires specific setup and hold times to properly latch data through the data interface bus. These timing parameters are specified relative to an internally generated output reference clock. The AD9861 has two interface clocks provided through the IFACE3 and IFACE2 pins. The transmit timing specifications, setup and hold time, provide a minimum required window of valid data. Setup time (tSETUP) is the time required for data to initially settle to a valid logic level prior to the relative output timing edge. Hold time (tHOLD) is the time after the output timing edge that valid data must remain on the data bus to be properly latched. Figure 85 shows tSETUP and tHOLD relative to IFACE3 falling edge. Note that in some cases negative time is specified, for example with tHOLD timing, which means that the hold time edge occurs before the relative output clock edge.
tSETUP tHOLD
IFACE3 (CLKOUT) Tx DATA
03606-0-028
Table 24. AD9861 Typical Tx Data Latch Timing Relative to IFACE3 Falling Edge
Mode No. 1 2 4 5 7 8 10 Mode Name FD Optional FD HD20 Optional HD20 HD10 Optional HD10 Clone tsetup (ns) 5 5 5 5 5 5 5 thold (ns) -2.5 -2.5 -1.5 -1.5 -2.5 -2.5 -1.5
Receive (Rx) path data is output after a reference output clock edge. The time delay of the Rx data relative to a reference output clock is called the output delay, tOD. The AD9861 has two possible interface clocks provided through the IFACE3 and IFACE2 pins. Figure 86 shows tOD relative to IFACE3 rising edge. Note that in some cases negative time is specified, which means that the output data transition occurs prior to the relative output clock edge.
tOD
IFACE3 (CLKOUT) Rx DATA
03606-0-029
Figure 85. Tx Data Timing Diagram
Table 24 shows typical setup-and-hold times for the AD9861 in the various mode configurations.
Figure 86. Rx Data Timing Diagram
Rev. 0 | Page 47 of 52
AD9861
Table 25 shows typical output delay times for the AD9861 in the various mode configurations.
Table 25. AD9861 Rx Data Latch Timing
Mode No. 1 2 4 5 7 8 10 Mode Name FD Optional FD HD20 Optional HD20 HD10 Optional HD10 Clone tOD Data Delay [ns] +2.5 ns +1 ns +1 ns +2 ns -1.5 ns -0.5 ns -1.5 ns +0.5 ns +0 ns +1.5 ns Relative to: Relative to IFACE2 rising edge Relative to IFACE3 rising edge Relative To IFACE3 rising edge IFACE2 (RxSYNC) relative to LSB Relative to IFACE3 rising edge Relative to IFACE3 rising edge Relative to IFACE3 rising edge Relative to IFACE3 rising edge U12 (RxSYNC) relative to LSB Relative to IFACE3 rising edge
Configuration without Serial Port Interface (Using Mode Pins)
The AD9861 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the AD9861 without an SPI. Refer is the Digital Block, Configuring with Mode Pins section for further information. When using the mode pin option, the pins shown in Table 26 are used to configured the AD9861.
Table 26. Using Mode Pin (SPI Disabled) to Configure Timing (SPI_CS, Pin 64, Must Be Tied Low)
Clock Mode Mode 1 (FD) Mode 4 (HD20) Interpolation Setting 2x 4x 1x 2x 4x 2x 4x PLL Setting 2x 4x Bypassed 2x 4x 2x 4x FD/HD Pin 3 1 0 10/20 Pin 17 N/A1 0 Interp1,Interp0 Pin 1, Pin 2 0, 1 1, 0 0, 0 0, 1 1, 0 0, 1 1, 0
Mode 7 (HD10)
1
0
1
Pin 17 (IFACE2) is an output clock in FD mode.
Rev. 0 | Page 48 of 52
AD9861 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
BOTTOM VIEW
7.25 7.10 SQ* 6.95
0.45 0.40 0.35
33 32
17
16
0.25 MIN 7.50 REF 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF
* COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION
Figure 87. 64-Lead Lead Frame Chip Scale Package (LFCSP) [CP-64]
Rev. 0 | Page 49 of 52
AD9861
ORDERING GUIDE
Model AD9861BCP-50 AD9861BCP-80 AD9861BCPRL-50 AD9861BCPRL-80 AD9861-50EB AD9861-80EB Temperature Range -40C to +85C (Ambient) -40C to +85C (Ambient) -40C to +85C (Ambient) -40C to +85C (Ambient) 25C (Ambient) 25C (Ambient) Package Description 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP Evaluation Board Evaluation Board Package Option CP-64 CP-64 CP-64 CP-64
Rev. 0 | Page 50 of 52
AD9861 NOTES
Rev. 0 | Page 51 of 52
AD9861 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03606-0-11/03(0)
Rev. 0 | Page 52 of 52

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